Patents by Inventor Hung-Chih Ou
Hung-Chih Ou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942941Abstract: A device including a first supply voltage track, a second supply voltage track, a first reference track, a first standard cell, and a second standard cell. The first supply voltage track is configured to provide a first voltage and the second supply voltage track is configured to provide a second voltage that is greater than the first voltage. The first standard cell is configured to be electrically connected to the first supply voltage track to receive the first voltage and electrically connected to the first reference track. The second standard cell is configured to be electrically connected to the second supply voltage track to receive the second voltage and electrically connected to the first reference track.Type: GrantFiled: July 26, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chih Ou, Wen-Hao Chen
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Patent number: 11934763Abstract: A semiconductor device includes a first circuit element, a layer of dielectric material, a first wire and a second wire in the layer of dielectric material, and an array of wires in the layer of dielectric material, wherein a first wire at a first track in the array of wires is electrically connected to the first circuit element, the first wire having a first width, a second wire at a second track in the array of wires has a second width different from the first width, and a third track in the array of wires between the first track and the second track is an empty track, and wherein the first wire is asymmetric with respect to the first track in the array of wires.Type: GrantFiled: November 9, 2020Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chih Ou, Wen-Hao Chen
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Patent number: 11928416Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.Type: GrantFiled: March 1, 2023Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chih Ou, Kuo-Fu Lee, Wen-Hao Chen, Keh-Jeng Chang, Hsiang-Ho Chang
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Publication number: 20240039518Abstract: A device including a first supply voltage track, a second supply voltage track, a first reference track, a first standard cell, and a second standard cell. The first supply voltage track is configured to provide a first voltage and the second supply voltage track is configured to provide a second voltage that is greater than the first voltage. The first standard cell is configured to be electrically connected to the first supply voltage track to receive the first voltage and electrically connected to the first reference track. The second standard cell is configured to be electrically connected to the second supply voltage track to receive the second voltage and electrically connected to the first reference track.Type: ApplicationFiled: July 26, 2022Publication date: February 1, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chih Ou, Wen-Hao Chen
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Publication number: 20230334219Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability, and includes a first reset pin configured to receive a first reset signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second reset pin configured to receive the first reset signal, and the first reset pin and the second reset pin are coupled together. The first inverter is configured to receive a first clock signal on a first clock pin, and configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.Type: ApplicationFiled: June 19, 2023Publication date: October 19, 2023Inventors: Sheng-Hsiung CHEN, Wen-Hao CHEN, Hung-Chih OU, Chun-Yao KU, Shao-Huan WANG
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Patent number: 11727185Abstract: A system includes a non-transitory computer readable medium configured to store instructions thereon. The system further includes a processor connected to the non-transitory computer readable medium. The processor is configured to execute the instruction for comparing a size of a via pillar structure of a first layout pattern of a plurality of layout patterns with a size of a via pillar structure of a second layout pattern of the plurality of layout patterns, wherein each of the plurality of layout patterns meets an electromigration (EM) rule. The processor is further configured to execute the instructions for replacing, in a layout design, the first layout pattern with the second layout pattern in response to the size of the via pillar structure of the second layout pattern being less than the size of the via pillar structure of the first layout pattern.Type: GrantFiled: July 26, 2022Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shao-Huan Wang, Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Chen Chen, Hung-Chih Ou
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Publication number: 20230205974Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.Type: ApplicationFiled: March 1, 2023Publication date: June 29, 2023Inventors: Hung-Chih Ou, Kuo-Fu Lee, Wen-Hao Chen, Keh-Jeng Chang, Hsiang-Ho Chang
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Patent number: 11681853Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.Type: GrantFiled: March 11, 2022Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Hsiung Chen, Wen-Hao Chen, Hung-Chih Ou, Chun-Yao Ku, Shao-Huan Wang
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Patent number: 11604915Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.Type: GrantFiled: April 15, 2021Date of Patent: March 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Hung-Chih Ou, Kuo-Fu Lee, Wen-Hao Chen, Keh-Jeng Chang, Hsiang-Ho Chang
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Publication number: 20230014110Abstract: A device including first track groups on a first conductive layer of an integrated circuit. Each of the first track groups including at least one of a different first track group pitch, a different first track group spacing, and a different first track group width than the other first track groups. Where each of the first track groups includes first tracks that have at least one of a different first track width and a different first track spacing than the first tracks in the other first track groups.Type: ApplicationFiled: February 9, 2022Publication date: January 19, 2023Inventors: Hung-Chih Ou, Wen-Hao Chen
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Publication number: 20220358277Abstract: A system includes a non-transitory computer readable medium configured to store instructions thereon. The system further includes a processor connected to the non-transitory computer readable medium. The processor is configured to execute the instruction for comparing a size of a via pillar structure of a first layout pattern of a plurality of layout patterns with a size of a via pillar structure of a second layout pattern of the plurality of layout patterns, wherein each of the plurality of layout patterns meets an electromigration (EM) rule. The processor is further configured to execute the instructions for replacing, in a layout design, the first layout pattern with the second layout pattern in response to the size of the via pillar structure of the second layout pattern being less than the size of the via pillar structure of the first layout pattern.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Shao-Huan WANG, Sheng-Hsiung CHEN, Wen-Hao CHEN, Chun-Chen CHEN, Hung-Chih OU
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Publication number: 20220335196Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.Type: ApplicationFiled: April 15, 2021Publication date: October 20, 2022Inventors: Hung-Chih Ou, Kuo-Fu Lee, Wen-Hao Chen, Keh-Jeng Chang, Hsiang-Ho Chang
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Patent number: 11449656Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.Type: GrantFiled: September 23, 2020Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shao-Huan Wang, Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Chen Chen, Hung-Chih Ou
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Publication number: 20220198122Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.Type: ApplicationFiled: March 11, 2022Publication date: June 23, 2022Inventors: Sheng-Hsiung CHEN, Wen-Hao CHEN, Hung-Chih OU, Chun-Yao KU, Shao-Huan WANG
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Publication number: 20220147687Abstract: A discrete multi-row height cell in a hybrid row-height system with a plurality of rows of at least two different row-heights is disclosed. The discrete multi-row height cell includes: a first sub-cell deployed on a first row with a first row-height; a second sub-cell deployed on a second row with a second row-height, wherein the second row and the first row is separated by a third row with a third row-height, wherein the third row-height is different from the first row-height, wherein the first sub-cell and the second sub-cell are electrically connected by at least a wire.Type: ApplicationFiled: January 21, 2022Publication date: May 12, 2022Inventors: Hung-Chih Ou, Wen-Hao Chen, Chun-Yao Ku
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Patent number: 11275886Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop, a first inverter, and a second inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The second inverter is coupled to the first inverter, is configured to receive the second clock signal, and is configured to generate a third clock signal inverted from the second clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.Type: GrantFiled: April 20, 2021Date of Patent: March 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Yao Ku, Shao-Huan Wang, Hung-Chih Ou
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Patent number: 11263378Abstract: A discrete multi-row height cell in a hybrid row-height system with a plurality of rows of at least two different row-heights is disclosed. The discrete multi-row height cell includes: a first sub-cell deployed on a first row with a first row-height; a second sub-cell deployed on a second row with a second row-height, wherein the second row and the first row is separated by a third row with a third row-height, wherein the third row-height is different from the first row-height, wherein the first sub-cell and the second sub-cell are electrically connected by at least a wire.Type: GrantFiled: January 16, 2020Date of Patent: March 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hung-Chih Ou, Wen-Hao Chen, Chun-Yao Ku
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Publication number: 20210256193Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop, a first inverter, and a second inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The second inverter is coupled to the first inverter, is configured to receive the second clock signal, and is configured to generate a third clock signal inverted from the second clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.Type: ApplicationFiled: April 20, 2021Publication date: August 19, 2021Inventors: Sheng-Hsiung CHEN, Wen-Hao CHEN, Chun-Yao KU, Shao-Huan WANG, Hung-Chih OU
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Patent number: 11087061Abstract: A method, a non-transitory computer-readable storage medium and a system for a design layout are provided. The method includes: receiving a design layout including a first cell and a second cell; providing a conductive member electrically connected between the first cell and the second cell, the conductive member including a first conductive line and a second conductive line parallel to the first conductive line; determining a first merging point in the first conductive line between the first cell and the second cell; and electrically connecting the first conductive line to the second conductive line at the first merging point.Type: GrantFiled: March 20, 2020Date of Patent: August 10, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hung-Chih Ou, Wen-Hao Chen
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Publication number: 20210224455Abstract: A discrete multi-row height cell in a hybrid row-height system with a plurality of rows of at least two different row-heights is disclosed. The discrete multi-row height cell includes: a first sub-cell deployed on a first row with a first row-height; a second sub-cell deployed on a second row with a second row-height, wherein the second row and the first row is separated by a third row with a third row-height, wherein the third row-height is different from the first row-height, wherein the first sub-cell and the second sub-cell are electrically connected by at least a wire.Type: ApplicationFiled: January 16, 2020Publication date: July 22, 2021Inventors: Hung-Chih Ou, Wen-Hao Chen, Chun-Yao Ku