Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a layer stack over a substrate, where the layer stack includes alternating layers of a first dielectric material and a word line (WL) material; forming first trenches extending vertically through the layer stack; filling the first trenches, where filling the first trenches includes forming, in the first trenches, a ferroelectric material, a channel material over the ferroelectric material, and a second dielectric material over the channel material; after filling the first trenches, forming second trenches extending vertically through the layer stack, the second trenches being interleaved with the first trenches; and filling the second trenches, where filling the second trenches includes forming, in the second trenches, the ferroelectric material, the channel material over the ferroelectric material, and the second dielectric material over the channel material.

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming, over a substrate, a layer stack having alternating layers of a first conductive material and a first dielectric material; forming trenches extending vertically through the layer stack from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate; lining sidewalls and bottoms of the trenches with a memory film; forming a channel material over the memory film, the channel material including an amorphous material; filling the trenches with a second dielectric material after forming the channel material; forming memory cell isolation regions in the second dielectric material; forming source lines (SLs) and bit lines (BLs) that extend vertically in the second dielectric material on opposing sides of the memory cell isolation regions; and crystallizing first portions of the channel material after forming the SLs and BLs.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: In a display driving circuit, odd-stage shift registers (SRs) are cascaded; and even-stage SRs are cascaded. The SRs support dual direction shifting. Each SR includes: first, second, third, and fourth transistors. The first transistor is coupled to a forward scan start signal from a third transistor of a former second SR, coupled to an output signal from the former second SR and coupled to a node. The second transistor is coupled to a reverse scan start signal from a fourth transistor of a next second SR, coupled to an output signal from the next second SR and coupled to the node. The third transistor is coupled to a forward operation voltage and coupled to the node, and further outputs a forward scan start signal. The fourth transistor is coupled to a reverse operation voltage and coupled to the node, and further outputs a reverse scan start signal.

Abstract: A stereoscopic display apparatus is cooperated with a shutter apparatus. The stereoscopic display apparatus includes a display module and an infrared emitting device. The display module has a viewable area and an optical sheet. The infrared emitting device is disposed in the display module. The light emitted from the infrared emitting device passes through the optical sheet and the viewable area and be received by the shutter apparatus to control it. The stereoscopic display apparatus can reduce the cost and make the appearance of the stereoscopic display apparatus have better integrity.

Abstract: In a display driving circuit, odd-stage shift registers (SRs) are cascaded; and even-stage SRs are cascaded. The SRs support dual direction shifting. Each SR includes: first, second, third, and fourth transistors. The first transistor is coupled to a forward scan start signal from a third transistor of a former second SR, coupled to an output signal from the former second SR and coupled to a node. The second transistor is coupled to a reverse scan start signal from a fourth transistor of a next second SR, coupled to an output signal from the next second SR and coupled to the node. The third transistor is coupled to a forward operation voltage and coupled to the node, and further outputs a forward scan start signal. The fourth transistor is coupled to a reverse operation voltage and coupled to the node, and further outputs a reverse scan start signal.