Abstract: An apparatus is disclosed for a charge pump with voltage tracking. In an example aspect, the apparatus includes a locked loop having a charge pump, a filter, a second switch, and a buffer. The charge pump includes a first current source, a second current source, and a first switch coupled between the first current source and the second current source. The filter is coupled to the charge pump between the first switch and the second current source. The second switch is coupled to the charge pump between the first current source and the first switch. The buffer is coupled between the filter and the second switch, with the buffer comprising a voltage buffer.

Abstract: A switched capacitance circuit selectively provides a capacitance across first and second output nodes in response to a selection control signal. The switched capacitance circuit may include a first capacitor coupled between the first output node and a mid-node, a second capacitor coupled between the second output node and the mid-node, and a switching circuit. The switching circuit is configured to switch the first and second capacitors in response to the selection control signal and to provide a bias voltage at the mid-node in response to the selection control signal.

Abstract: A switched capacitance circuit selectively provides a capacitance across first and second output nodes in response to a selection control signal. The switched capacitance circuit may include a first capacitor coupled between the first output node and a mid-node, a second capacitor coupled between the second output node and the mid-node, and a switching circuit. The switching circuit is configured to switch the first and second capacitors in response to the selection control signal and to provide a bias voltage at the mid-node in response to the selection control signal.

Abstract: Aspects of a reconfigurable frequency divider circuit are provided. A reconfigurable frequency divider can include a frequency divider that is configured to receive an input signal. The frequency divider can also include a delay circuit that is configured to receive a divided signal produced by the frequency divider. The frequency divider can also include a frequency multiplier that is configured to produce an output signal based on the delayed signal produced by the delay circuit, wherein the delay circuit is configured to receive the output signal.

Abstract: A low-noise amplifier accepts a single-ended input signal at an input port and provides a differential output signal at an output port. Each of a pair of transistors in the amplifier has a pair of input terminals and a pair of output terminals that share a common terminal. A feedback circuit is electrically connected between the non-common output terminal and the non-common input terminal of a closed-loop one of the transistors and is electrically disconnected from any two terminals of an open-loop one of the transistors. The input port has a signal-carrying input terminal electrically connected to the non-common input terminal of both of the transistors and a ground terminal. The output port has a positive terminal electrically connected to the common terminal of the open-loop transistor and a negative terminal electrically connected to non-common output terminal of the closed-loop transistor.

Abstract: Aspects of a reconfigurable frequency divider circuit are provided. A reconfigurable frequency divider can include a frequency divider that is configured to receive an input signal. The frequency divider can also include a delay circuit that is configured to receive a divided signal produced by the frequency divider. The frequency divider can also include a frequency multiplier that is configured to produce an output signal based on the delayed signal produced by the delay circuit, wherein the delay circuit is configured to receive the output signal.

Abstract: A variable-gain low-noise amplifier (VG-LNA) accepts a single-ended input signal at an input port and provides a differential output signal at an output port. The VG-LNA includes amplifier stages that are commonly coupled to the input port, with subtrahend amplifier stages commonly coupled to a negative terminal of the output port and minuend amplifier stages commonly coupled to a positive terminal of the output port. A control circuit activates up to one of the subtrahend amplifier stages and one of the minuend amplifier stages as a differential set of amplifier stages that generates the differential output signal from the single-ended input signal.

Abstract: A low-noise amplifier accepts a single-ended input signal at an input port and provides a differential output signal at an output port. Each of a pair of transistors in the amplifier has a pair of input terminals and a pair of output terminals that share a common terminal. A feedback circuit is electrically connected between the non-common output terminal and the non-common input terminal of a closed-loop one of the transistors and is electrically disconnected from any two terminals of an open-loop one of the transistors. The input port has a signal-carrying input terminal electrically connected to the non-common input terminal of both of the transistors and a ground terminal. The output port has a positive terminal electrically connected to the common terminal of the open-loop transistor and a negative terminal electrically connected to non-common output terminal of the closed-loop transistor.

Abstract: A variable-gain low-noise amplifier (VG-LNA) accepts a single-ended input signal at an input port and provides a differential output signal at an output port. The VG-LNA includes amplifier stages that are commonly coupled to the input port, with subtrahend amplifier stages commonly coupled to a negative terminal of the output port and minuend amplifier stages commonly coupled to a positive terminal of the output port. A control circuit activates up to one of the subtrahend amplifier stages and one of the minuend amplifier stages as a differential set of amplifier stages that generates the differential output signal from the single-ended input signal.

Abstract: An amplifier for wireless receivers and an associated method is provided. The amplifier provides an output signal to an output terminal in response to an input signal received from an input terminal, and further includes a first block and a second block. The first block is coupled between the input terminal and the output terminal, and includes a gain control terminal and a first transistor. The gain control terminal is coupled to a gain control signal, while the gain control signal is provided such that the first transistor is kept operating in a triode region, and a gain of the output signal over the input signal can be seamlessly tuned in response to the gain control signal.

Abstract: An amplifier for wireless receivers and an associated method is provided. The amplifier provides an output signal to an output terminal in response to an input signal received from an input terminal, and further includes a first block and a second block. The first block is coupled between the input terminal and the output terminal, and includes a gain control terminal and a first transistor. The gain control terminal is coupled to a gain control signal, while the gain control signal is provided such that the first transistor is kept operating in a triode region, and a gain of the output signal over the input signal can be seamlessly tuned in response to the gain control signal.

Abstract: The invention discloses an interference cancellation circuit for a receiver to process an input signal which is carried on a first carrier frequency and includes a transmitted signal and at least one interference signals. The interference cancellation circuit comprises a down-converter for converting the input signal to dc location to generate a down-converted signal; a first path circuit for processing the down-converted signal to generate a first processed signal which includes the transmitted signal and the interference signals; a second path circuit for processing the down-converted signal to generate a second processed signal which includes only the interference signals; and a combiner for generating an output signal by combining the first processed signal and the second processed signal.

Abstract: A fingerprint sensing circuit for detecting a fingerprint of a user, including a signal source, at least a sensing unit, a resistor, an electrode, and a detecting circuit. The signal source provides a reference signal. The electrode is coupled to a reference level. The sensing unit generates a sensed value according to the electrode and the fingerprint of the user. The resistor is coupled between the signal source and the output node. The detecting circuit is coupled to the output node. The resistor, the sensing unit, and the electrode constitute a filter circuit to the signal source. At least a first signal is generated to the output node according to the reference signal and the sensed value, and the detecting circuit detects the first signal to generate a corresponding detected result indicative of the fingerprint.

Abstract: The invention discloses an interference cancellation circuit for a receiver to process an input signal which is carried on a first carrier frequency and includes a transmitted signal and at least one interference signals. The interference cancellation circuit comprises a down-converter for converting the input signal to dc location to generate a down-converted signal; a first path circuit for processing the down-converted signal to generate a first processed signal which includes the transmitted signal and the interference signals; a second path circuit for processing the down-converted signal to generate a second processed signal which includes only the interference signals; and a combiner for generating an output signal by combining the first processed signal and the second processed signal.

Abstract: A sigma-delta modulator includes a loop filter, a single bit quantizer, a single bit DAC, an adder. The loop filter is for filtering a summed signal to generate a filtered signal. The single bit quantizer is coupled to the loop filter, for performing a quantization process to the filtered signal to generate a quantized signal. The single bit DAC is coupled to the single bit quantizer, has an adjustable configuration, and is for generating a feedback signal according to the quantized signal and the configuration thereof. The adder is coupled to the loop filter and the single bit DAC, for summing an input signal and the feedback signal to generate the summed signal.

Abstract: A sigma-delta modulator includes a loop filter, a single bit quantizer, a single bit DAC, an adder. The loop filter is for filtering a summed signal to generate a filtered signal. The single bit quantizer is coupled to the loop filter, for performing a quantization process to the filtered signal to generate a quantized signal. The single bit DAC is coupled to the single bit quantizer, has an adjustable configuration, and is for generating a feedback signal according to the quantized signal and the configuration thereof. The adder is coupled to the loop filter and the single bit DAC, for summing an input signal and the feedback signal to generate the summed signal.

Abstract: A fingerprint sensing circuit for detecting a fingerprint of a user, including a signal source, at least a sensing unit, a resistor, an electrode, and a detecting circuit. The signal source provides a reference signal. The electrode is coupled to a reference level. The sensing unit generates a sensed value according to the electrode and the fingerprint of the user. The resistor is coupled between the signal source and the output node. The detecting circuit is coupled to the output node. The resistor, the sensing unit, and the electrode constitute a filter circuit to the signal source. At least a first signal is generated to the output node according to the reference signal and the sensed value, and the detecting circuit detects the first signal to generate a corresponding detected result indicative of the fingerprint.

Abstract: A high order continuous-time Sigma-Delta Modulator (??M) is used for its high carrier-to-noise ratio (CNR) performance and low power consumption. The modulator is designed to allow zero-IF, wide-band low-pass or low-IF flexibility. The sigma-delta ADC modulator includes a receiving circuit, a plurality of loop filter transconductors, a plurality of feedforward weighting amplifiers, a first adding element, at least a local feedback circuit, a quantizer, and a feedback DAC. The local feedback circuit includes a feedback weighting amplifier and a second adding element. The feedback coefficient of the feedback weighting amplifier is tunable, and the local feedback circuits can be designed to maximize bandwidth combination.

Abstract: An offset correction analogic circuit capable of compensating the offset of a digital baseband is described. The circuit comprises analog means to receive an output differential signal issued from a differential signal path. The differential signal path may be a baseband filter as used in digital communication systems. The baseband filter inputs an input differential signal having an offset to be compensated. The output differential signal is fed into an analog integrator to generate a pulsed signal either on a first output line or on a second output line according to the polarity of the output differential signal. The pulsed signal is then integrated into a switched capacitor and a differential compensation offset signal is issued. The frequency of the pulsed signal is preferably proportional to the voltage value of the output differential signal. The compensation offset signal may be summed with the input differential signal into a summing circuit.

Abstract: Two reference signals are applied to an RC calibration circuit, which utilizes programmable resistors and switched capacitor resistors in parallel at the inputs of a differential amplifier with feedback capacitors, for the first cycle and then the two reference signals are swapped for the successive cycle. The circuit inherent DC offset is cancelled by these two successive cycles. The time duration when the difference of the differential amplifier outputs in the calibration circuit starts to reverse ramping direction and the time when the difference crosses zero is counted in terms of reference clock cycles by a binary counter. The binary count is used to select the capacitance of the capacitor arrays in an RC filter for time constant calibration. This calibration circuit provides the flexibility for various reference clock rates by adjusting the programmable resistors.