Abstract: Composite dielectric structures for semiconductor die assemblies, and associated systems and methods are disclosed. In some embodiments, the composite dielectric structure includes a flexible dielectric layer configured to conform to irregularities (e.g., particles, defects) at a bonding interface of directly bonded semiconductor dies (or wafers). The flexible dielectric layer may include a polymer material configured to deform in response to localized pressure generated by the irregularities during bonding process steps. The composite dielectric structure includes additional dielectric layers sandwiching the flexible dielectric layer such that the composite dielectric structure can provide robust bonding strength to other dielectric layers through the additional dielectric layers. In some embodiments, a chemical vapor deposition process may be used to form the composite dielectric structure utilizing siloxane derivatives as a precursor.

Abstract: A multi-phase coupled inductor includes a first iron core, a second iron core, and a plurality of coil windings. The first iron core includes a first body and a plurality of first core posts. The plurality of first core posts are connected to the first body. The second iron core is opposite to the first iron core. The second iron core and the first body are spaced apart from each other by a gap. The plurality of coil windings wrap around the plurality of first core posts, respectively. Each of the coil windings has at least two coils.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

Abstract: A package structure and method of forming the same are provided. The package structure includes a polymer layer, a redistribution layer, a die, and an adhesion promoter layer. The redistribution layer is disposed over the polymer layer. The die is sandwiched between the polymer layer and the redistribution layer. The adhesion promoter layer, an oxide layer, a through via, and an encapsulant are sandwiched between the polymer layer and the redistribution layer. The encapsulant is laterally encapsulates the die. The through via extends through the encapsulant. The adhesion promoter layer and the oxide layer are laterally sandwiched between the through via and the encapsulant. A bottom portion of the encapsulant is longitudinally sandwiched between the adhesion promoter layer and the polymer layer.

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.

Abstract: In an example embodiment, a method comprising identifying, by a primary-side controlled Universal Serial Bus Power Delivery (USB-PD) alternating current to direct current (AC-DC) converter, a first pulse, wherein the first pulse is received from a pulse transformer. The method further includes determining that a threshold duration of time is satisfied. In response to determining that the threshold duration of time is satisfied, the method includes identifying a second pulse, wherein the second pulse is received from the pulse transformer. The first pulse and the second pulse are used for control of a high-side field effect transistor (FET) and a low-side FET, where the high-side FET is coupled to an active clamp flyback (ACF) circuit and the low-side FET is coupled to a flyback transformer of the USB-PD AC-DC converter. In response to identifying the second pulse, the method further includes controlling operation of the high-side FET or the low-side FET.

Abstract: A method for forming a semiconductor device includes followings. A metal layer is formed to embedded in a first dielectric layer. An etch stop layer is formed over the metal layer and the first dielectric layer. A second dielectric layer is formed over the etch stop layer. A portion of the second dielectric layer is removed to expose a portion of the etch stop layer and to form a via by a dry etching process. The portion of the etch stop layer exposed by the second dielectric layer is removed to expose the metal layer and to form a damascene cavity by a wet etching process. A damascene structure is formed in the damascene cavity.

Abstract: A floor frame includes at least two spaced longitudinal support strips and at least one lateral support strip. Each longitudinal support strip has longitudinal upper and lower portions and a pair of longitudinal side walls. A shoulder is designed on at least one of the pair longitudinal side walls and located between the longitudinal upper and lower portions. Two shoulders of the two longitudinal support strips are opposite to each other. The lateral support strip includes lateral upper and lower portions and a pair of lateral side walls. Two ends of the lateral support strip are placed on the two shoulders of the longitudinal support strips, respectively. A plurality of longitudinal and lateral support strips constitutes a grid-type structure under the distribution of longitudinal and lateral directions to provide the placement and fixation of a plurality of floor panels.

Abstract: A certificate management system includes an electronic device and a server. The electronic device is configured to transmit a certificate application request. The server is configured to sign a device certificate corresponding to the electronic device through an intermediate certificate device after receiving the certificate application request, and transmit the device certificate and the Internet address of the server to the electronic device. The electronic device stores the device certificate and the Internet address of the server to complete the certificate issuance operation.

Abstract: A certificate transfer system includes a first certificate management host and a certificate transfer management host. The first certificate management host is configured to generate a first certificate, sign an electronic device with the first certificate, and transmit a first Internet address to the electronic device to complete a certificate-issuance operation. The certificate transfer management host is configured to store a transfer device list and a second Internet address. When the first certificate management host receives the first certificate issued by the electronic device, the first certificate management host verifies that the first certificate is correct and determines that if the first certificate matches one of the certificates in the transfer device list, the first certificate management host returns the certificate transfer management host address to the electronic device.

Abstract: A floor frame includes at least two spaced longitudinal support strips and at least one lateral support strip. Each longitudinal support strip has longitudinal upper and lower portions and a pair of longitudinal side walls. A shoulder is designed on at least one of the pair longitudinal side walls and located between the longitudinal upper and lower portions. Two shoulders of the two longitudinal support strips are opposite to each other. The lateral support strip includes lateral upper and lower portions and a pair of lateral side walls. Two ends of the lateral support strip are placed on the two shoulders of the longitudinal support strips, respectively. A plurality of longitudinal and lateral support strips constitutes a grid-type structure under the distribution of longitudinal and lateral directions to provide the placement and fixation of a plurality of floor panels.

Abstract: A certificate transfer system includes a first certificate management host and a certificate transfer management host. The first certificate management host is configured to generate a first certificate, sign an electronic device with the first certificate, and transmit a first Internet address to the electronic device to complete a certificate-issuance operation. The certificate transfer management host is configured to store a transfer device list and a second Internet address. When the first certificate management host receives the first certificate issued by the electronic device, the first certificate management host verifies that the first certificate is correct and determines that if the first certificate matches one of the certificates in the transfer device list, the first certificate management host returns the certificate transfer management host address to the electronic device.

Abstract: A certificate management system includes an electronic device and a server. The electronic device is configured to transmit a certificate application request. The server is configured to sign a device certificate corresponding to the electronic device through an intermediate certificate device after receiving the certificate application request, and transmit the device certificate and the Internet address of the server to the electronic device. The electronic device stores the device certificate and the Internet address of the server to complete the certificate issuance operation.

Abstract: A lens driving mechanism is provided, including a lens holder for holding a lens, a circuit board disposed at one side of the lens holder, a driving element, a position sensing element and an integrated circuit module. The position sensing element and the integrated circuit module are disposed on the circuit board, wherein the integrated circuit module includes a driving circuit unit electrically connected to the driving element, to move the lens holder relative to the circuit board.

Abstract: An apparatus for detecting an object capable of emitting light. The apparatus comprises a light detector comprising at least two optical sensors capable of determining the intensity of the light; and a computer processing output signal generated by the optical sensors and comparing a result of the processing with a known result corresponding to a known type to determine whether the object belongs to the known type.

Abstract: A lens driving mechanism is provided, including a lens holder, a circuit unit, a driving element, and an integrated circuit element. The lens holder is used for holding a lens. The circuit unit is disposed on a side of the lens holder. The driving element is used for driving the lens holder to move relative to the circuit unit. The integrated circuit element is electrically connected to the driving element and disposed on the circuit unit. The driving element is disposed between the lens holder and the integrated circuit element.

Abstract: An illuminating device includes an insulative housing, at least two electrodes and a light source. The insulative housing has opposite front and rear surfaces and is formed with at least two through holes. Each of the through holes is defined by a hole wall and penetrates the front and rear surfaces. Each of the electrodes includes a first conductive segment formed proximate the front surface, a second conductive segment formed proximate the rear surface, and a connecting segment formed inside a respective one of the through holes and interconnecting electrically the first and second conductive segments. The light source is disposed on the front surface and includes first and second connecting terminals each being electrically coupled to the first conductive segment of a corresponding one of the electrodes.