Patents by Inventor Hung Chun Chiu

Hung Chun Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10797226
    Abstract: A magnetoresistive memory cell is provided including a substrate. An inter-layer dielectric layer is disposed on the substrate. A via structure is disposed in the inter-layer dielectric layer. A magnetic pinned layer is disposed on the via structure. A tunnel barrier layer is disposed on the magnetic pinned layer to cover a top and a sidewall of the magnetic pinned layer, wherein the tunnel barrier layer comprises a horizontal extending portion outward from a bottom of the sidewall. A magnetic free layer with a -like structure is disposed on the tunnel barrier layer, wherein the magnetic free layer is isolated from the magnetic pinned layer by the tunnel bather layer. A spacer is disposed on the sidewall of the magnetic free layer. The spacer extends to the inter-layer dielectric layer.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: October 6, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Sheng Feng, Yu-Chun Chen, Chiu-Jung Chiu, Hung-Chan Lin
  • Publication number: 20200243753
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the MTJ, and a second spacer on another side of the MTJ, in which the first spacer and the second spacer are asymmetric. Specifically, the MTJ further includes a first bottom electrode disposed on a metal interconnection, a capping layer on the bottom electrode, and a top electrode on the capping layer, in which a top surface of the first spacer is even with a top surface of the top electrode and a top surface of the second spacer is lower than the top surface of the top electrode and higher than the top surface of the capping layer.
    Type: Application
    Filed: April 16, 2020
    Publication date: July 30, 2020
    Inventors: Yu-Chun Chen, Ya-Sheng Feng, Chiu-Jung Chiu, Hung-Chan Lin
  • Patent number: 10665772
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the MTJ, and a second spacer on another side of the MTJ, wherein the first spacer and the second spacer are asymmetric. Specifically, the MTJ further includes a first bottom electrode disposed on a metal interconnection, a capping layer on the bottom electrode, and a top electrode on the capping layer, in which a top surface of the first spacer is even with a top surface of the top electrode and a top surface of the second spacer is lower than the top surface of the top electrode and higher than the top surface of the capping layer.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 26, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Chun Chen, Ya-Sheng Feng, Chiu-Jung Chiu, Hung-Chan Lin
  • Patent number: 10629802
    Abstract: A magnetoresistance device is disclosed, comprising a bottom electrode, a magnetic tunneling junction (MTJ) disposed on the bottom electrode, a top electrode disposed on the magnetic tunneling junction, a first spacer disposed on the magnetic tunneling junction and covering a sidewall of the top electrode, and a second spacer disposed on the first spacer and conformally covering along a sidewall of the first spacer, a sidewall of the magnetic tunneling junction and a sidewall of the bottom electrode.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chiu-Jung Chiu, Yu-Chun Chen, Ya-Sheng Feng, Hung-Chan Lin
  • Publication number: 20200111950
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the MTJ, and a second spacer on another side of the MTJ, wherein the first spacer and the second spacer are asymmetric. Specifically, the MTJ further includes a first bottom electrode disposed on a metal interconnection, a capping layer on the bottom electrode, and a top electrode on the capping layer, in which a top surface of the first spacer is even with a top surface of the top electrode and a top surface of the second spacer is lower than the top surface of the top electrode and higher than the top surface of the capping layer.
    Type: Application
    Filed: November 1, 2018
    Publication date: April 9, 2020
    Inventors: Yu-Chun Chen, Ya-Sheng Feng, Chiu-Jung Chiu, Hung-Chan Lin
  • Publication number: 20200106000
    Abstract: A magnetoresistance device is disclosed, comprising a bottom electrode, a magnetic tunneling junction (MTJ) disposed on the bottom electrode, a top electrode disposed on the magnetic tunneling junction, a first spacer disposed on the magnetic tunneling junction and covering a sidewall of the top electrode, and a second spacer disposed on the first spacer and conformally covering along a sidewall of the first spacer, a sidewall of the magnetic tunneling junction and a sidewall of the bottom electrode.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 2, 2020
    Inventors: Chiu-Jung Chiu, Yu-Chun Chen, Ya-Sheng Feng, Hung-Chan Lin
  • Publication number: 20200075840
    Abstract: A magnetoresistive memory cell is provided including a substrate. An inter-layer dielectric layer is disposed on the substrate. A via structure is disposed in the inter-layer dielectric layer. A magnetic pinned layer is disposed on the via structure. A tunnel barrier layer is disposed on the magnetic pinned layer to cover a top and a sidewall of the magnetic pinned layer, wherein the tunnel barrier layer comprises a horizontal extending portion outward from a bottom of the sidewall. A magnetic free layer with a -like structure is disposed on the tunnel barrier layer, wherein the magnetic free layer is isolated from the magnetic pinned layer by the tunnel bather layer. A spacer is disposed on the sidewall of the magnetic free layer. The spacer extends to the inter-layer dielectric layer.
    Type: Application
    Filed: October 1, 2018
    Publication date: March 5, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Ya-Sheng Feng, Yu-Chun Chen, Chiu-Jung Chiu, Hung-Chan Lin
  • Publication number: 20200013949
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the first IMD layer; forming a liner on the MTJ and the first IMD layer; removing part of the liner to form a spacer adjacent to the MTJ; and forming a second IMD layer on the first IMD layer.
    Type: Application
    Filed: August 7, 2018
    Publication date: January 9, 2020
    Inventors: Ya-Sheng Feng, Hung-Chan Lin, Yu-Ping Wang, Yu-Chun Chen, Chiu-Jung Chiu
  • Patent number: 10529920
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the first IMD layer; forming a liner on the MTJ and the first IMD layer; removing part of the liner to form a spacer adjacent to the MTJ; and forming a second IMD layer on the first IMD layer.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: January 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Sheng Feng, Hung-Chan Lin, Yu-Ping Wang, Yu-Chun Chen, Chiu-Jung Chiu
  • Patent number: 9449138
    Abstract: A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes a non-transitory computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. A compilation is performed in accordance with a description file.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: September 20, 2016
    Assignee: Synopsys, Inc.
    Inventors: Yingtsai Chang, Sweyyan Shei, Hung-Chun Chiu, Meng-Chyi Lin, Hwa Mao, Ming-Yang Wang, Yu-Chin Hsu
  • Patent number: 9384313
    Abstract: User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: July 5, 2016
    Assignee: Synopsys, Inc.
    Inventors: Hung Chun Chiu, Meng-Chyi Lin, Kuen-Yang Tsai, Sweyyan Shei, Hwa Mao, Yingtsai Chang
  • Publication number: 20150294055
    Abstract: User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.
    Type: Application
    Filed: April 15, 2014
    Publication date: October 15, 2015
    Applicants: Synopsys, Inc., Synopsys Taiwan Co., Ltd.
    Inventors: Hung Chun Chiu, Meng-Chyi Lin, Kuen-Yang Tsai, Sweyyan Shei, Hwa Mao, Yingtsai Chang
  • Publication number: 20140351777
    Abstract: A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. The compilation is in accordance with a description file.
    Type: Application
    Filed: August 5, 2014
    Publication date: November 27, 2014
    Inventors: Yingtsai Chang, Sweyyan Shei, Hung-Chun Chiu, Meng-Chyi Lin, Hwa Mao, Ming-Yang Wang, Yu-Chin Hsu
  • Patent number: 8839179
    Abstract: A test system for testing prototype designs includes a host workstation, multiple interface devices, and multiple prototype boards. The prototype boards include programmable devices which implement one or more partitions of a user design and an associated verification modules. The verification modules probe signals of the partitions and transmit the probed signals to the interface devices. The verification modules can also transmit output signals generated by one or more partitions on the prototype boards to the host workstation via the interface devices, and transmit input signals, which are received from the host workstation via the interface devices, to one or more partitions on the prototype boards.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: September 16, 2014
    Assignee: Synopsys Taiwan Co., Ltd.
    Inventors: Yingtsai Chang, Sweyyan Shei, Hung-Chun Chiu, Meng-Chyi Lin, Hwa Mao, Ming Yang Wang, Yuchin Hsu
  • Patent number: 8739089
    Abstract: User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: May 27, 2014
    Assignees: Synopsys, Inc.
    Inventors: Hung Chun Chiu, Meng-Chyi Lin, Kuen-Yang Tsai, Sweyyan Shei, Hwa Mao, Yingtsai Chang
  • Patent number: 8732650
    Abstract: A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: May 20, 2014
    Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.
    Inventors: Yingtsai Chang, Sweyyan Shei, Hung Chun Chiu, Hwa Mao, Ming Yang Wang, Yuchin Hsu
  • Publication number: 20130055177
    Abstract: User's RTL design is analyzed and instrumented so that signals of interest are preserved and can be located in the net list after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the net list to ensure that signal values can be accessed at runtime. After that, a P&R process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in FPGAs. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.
    Type: Application
    Filed: August 28, 2012
    Publication date: February 28, 2013
    Applicants: SPRINGSOFT USA, INC., SPRINGSOFT, INC.
    Inventors: Hung Chun Chiu, Meng-Chyi Lin, Kuen-Yang Tsai, Sweyyan Shei, Hwa Mao, Yingtsai Chang
  • Publication number: 20130035925
    Abstract: A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation.
    Type: Application
    Filed: August 29, 2012
    Publication date: February 7, 2013
    Inventors: Yingtsai Chang, Sweyyan Shei, Hung Chun Chiu, Hwa Mao, Ming Yang Wang, Yuchin Hsu
  • Patent number: 7703054
    Abstract: A synthesizer processes a register transfer level (RTL) netlist description of a circuit to produce a non-optimized gate level netlist preserving all signals referenced by the RTL netlist. The gate level netlist is then processed to identify the circuit's memory devices and to determine logical relationships between its internal signals (all signals other than circuit and memory device input and output signals) and its other signals (circuit and memory device input and output signals). The synthesizer then again processes the RTL netlist to produce an optimized gate level netlist that preserves the identified memory devices, but which omits reference to some or all of the internal signals. A circuit verification system then processes the optimized gate level netlist to produce waveform data representing time-varying behavior of the other signals of the circuit.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: April 20, 2010
    Assignee: Springsoft, Inc.
    Inventors: Duan-Ping Chen, Sweyyan Shei, Hung Chun Chiu, Neu Choo Ngui, Ming Yang Wang
  • Publication number: 20080250378
    Abstract: A synthesizer processes a register transfer level (RTL) netlist description of a circuit to produce a non-optimized gate level netlist preserving all signals referenced by the RTL netlist. The gate level netlist is then processed to identify the circuit's memory devices and to determine logical relationships between its internal signals (all signals other than circuit and memory device input and output signals) and its other signals (circuit and memory device input and output signals). The synthesizer then again processes the RTL netlist to produce an optimized gate level netlist that preserves the identified memory devices, but which omits reference to some or all of the internal signals. A circuit verification system then processes the optimized gate level netlist to produce waveform data representing time-varying behavior of the other signals of the circuit.
    Type: Application
    Filed: April 9, 2007
    Publication date: October 9, 2008
    Inventors: Duan-Ping Chen, Sweyyan Shei, Hung Chun Chiu, Neu Choo Ngui, Ming Yang Wang