Patents by Inventor Hung Chun Tsai
Hung Chun Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240124350Abstract: A quantum dot composite structure and a method for forming the same are provided. The quantum dot composite structure includes: a glass particle including a glass matrix and a plurality of quantum dots located in the glass matrix, wherein at least one of the plurality of quantum dots includes an exposed surface in the glass matrix; and an inorganic protective layer disposed on the glass particle and covering the exposed surface.Type: ApplicationFiled: October 13, 2023Publication date: April 18, 2024Inventors: Ching LIU, Wen-Tse HUANG, Ru-Shi LIU, Pei Cong YAN, Chai-Chun HSIEH, Hung-Chun TONG, Yu-Chun LEE, Tzong-Liang TSAI
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Publication number: 20240120325Abstract: A stacked package structure and a manufacturing method thereof are provided. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected to the upper redistribution layer. The upper molding layer is disposed on the first chip and the upper redistribution layer, and is configured to package the first chip. The upper molding layer includes a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is circumferentially formed around a periphery of the upper molding layer.Type: ApplicationFiled: May 31, 2023Publication date: April 11, 2024Applicant: POWERTECH TECHNOLOGY INC.Inventors: Pei-chun TSAI, Hung-hsin HSU, Shang-yu CHANG CHIEN, Chia-ling LEE
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Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
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Patent number: 9219036Abstract: A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.Type: GrantFiled: April 6, 2015Date of Patent: December 22, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
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Publication number: 20150214159Abstract: A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.Type: ApplicationFiled: April 6, 2015Publication date: July 30, 2015Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
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Patent number: 8999842Abstract: A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.Type: GrantFiled: July 21, 2014Date of Patent: April 7, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
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Publication number: 20150017800Abstract: A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.Type: ApplicationFiled: July 21, 2014Publication date: January 15, 2015Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
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Patent number: 8785324Abstract: A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.Type: GrantFiled: December 10, 2012Date of Patent: July 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
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Patent number: 8330275Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.Type: GrantFiled: November 7, 2011Date of Patent: December 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
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Patent number: 8143162Abstract: An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide.Type: GrantFiled: July 10, 2009Date of Patent: March 27, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Yung-Cheng Lu, Hui-Lin Chang, Ting-Yu Shen, Hung Chun Tsai
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Publication number: 20120049371Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.Type: ApplicationFiled: November 7, 2011Publication date: March 1, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
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Patent number: 8101437Abstract: A method for manufacturing three-terminal solar cell array is provided. In this method, only four major scribing or etching steps are needed to expose the three conductive layers of the three-terminal solar cell and isolate the individual solar cells.Type: GrantFiled: December 29, 2010Date of Patent: January 24, 2012Assignee: Du Pont Apollo LimitedInventors: Hung-Chun Tsai, Liang-Ji Chen, Yu-Ting Lin, Yaw-Ming Tsai
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Publication number: 20110315215Abstract: The present invention provides a color backsheet for a building-integrated photovoltaic (BIPV) module comprising a polyethylene terephthalate (PET) film, a barrier layer and a fluorine-containing polymer film, at least one of the films being doped with dyes or pigments. The present invention also provides a color BIPV module comprising the color backsheet according to the present invention.Type: ApplicationFiled: June 27, 2011Publication date: December 29, 2011Applicant: DU PONT APOLLO LTD.Inventors: Liang-Jyi CHEN, Hung-Chun TSAI, Yu-Ting LIN
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Publication number: 20110315216Abstract: The present invention provides a color backsheet for a building-integrated photovoltaic (BIPV) module comprising a polyethylene terephthalate (PET) film and a fluorine-containing polymer film, at least one of the films being doped with dyes or pigments. The present invention also provides a color BIPV module comprising the color backsheet according to the present invention.Type: ApplicationFiled: June 27, 2011Publication date: December 29, 2011Applicant: DU PONT APOLLO LTD.Inventors: Liang-Jyi CHEN, Hung-Chun TSAI, Yu-Ting LIN
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Publication number: 20110308569Abstract: A multi-terminal solar panel includes a first substrate, a first solar cell layer, a transparent intercellular layer, a second solar cell layer and a second substrate. The first solar cell layer is disposed on the first substrate and has a first bandgap. The first solar cell layer includes two first terminal outputs, arranged substantially in parallel with each other, at two opposite edges thereof. The transparent intercellular layer is disposed on the first solar cell layer and exposes the two first terminal outputs. The second solar cell layer is disposed on the transparent intercellular layer and has a second bandgap. The second solar cell layer includes two second terminal outputs, arranged substantially in parallel with each other, at two opposite edges thereof. The second substrate is disposed on the second solar cell layer, wherein the two second terminal outputs are substantially perpendicular to the two first terminal outputs.Type: ApplicationFiled: June 20, 2011Publication date: December 22, 2011Applicant: Du Pont Apollo LimitedInventors: Hung-Chun TSAI, Liang-Ji Chen, Yu-Ting Lin, Yaw-Ming Tsai, Ker-Tai Chu
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Patent number: 8053356Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.Type: GrantFiled: October 12, 2010Date of Patent: November 8, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
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Publication number: 20110159629Abstract: A method for manufacturing three-terminal solar cell array is provided. In this method, only four major scribing or etching steps are needed to expose the three conductive layers of the three-terminal solar cell and isolate the individual solar cells.Type: ApplicationFiled: December 29, 2010Publication date: June 30, 2011Applicant: Du Pont Apollo LimitedInventors: Hung-Chun Tsai, Liang-Ji Chen, Yu-Ting Lin, Yaw-Ming Tsai
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Publication number: 20110155230Abstract: A multi-bandgap solar cell is produced by using a transparent intercellular layer to bind two solar cells with different bandgaps. The intercellular layer has at least an adhesive layer.Type: ApplicationFiled: December 10, 2010Publication date: June 30, 2011Applicant: Du Pont Apollo LimitedInventors: Hung-Chun Tsai, Chi-Lai Lee, Yu-Ting Lin, Yaw-Ming Tsai
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Publication number: 20110027991Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.Type: ApplicationFiled: October 12, 2010Publication date: February 3, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
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Patent number: 7834458Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.Type: GrantFiled: December 15, 2009Date of Patent: November 16, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang