Patents by Inventor Hung-Dar Wang

Hung-Dar Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8660276
    Abstract: A driving circuit for a sound outputting apparatus includes a H-bridge and a charge pump established by six switches for driving two types of loudspeakers, respectively. The six switches include two common switches to be configured in the H-bridge and the charge pump, thereby reducing the costs and circuit area of the driving circuit.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: February 25, 2014
    Assignee: Ricktek Technology Corp.
    Inventors: Chang-Chih Lin, Hung-Dar Wang, Pei-Cheng Huang
  • Publication number: 20120140958
    Abstract: A driving circuit for a sound outputting apparatus includes a H-bridge and a charge pump established by six switches for driving two types of loudspeakers, respectively. The six switches include two common switches to be configured in the H-bridge and the charge pump, thereby reducing the costs and circuit area of the driving circuit.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 7, 2012
    Applicant: RICHTEK TECHNOLOGY CORP.
    Inventors: Chang-Chih LIN, Hung-Dar WANG, Pei-Cheng HUANG
  • Patent number: 6967145
    Abstract: A method of maintaining photolithographic precision alignment for a wafer after being bonded, wherein two cavities are formed at the rear surface of a top wafer at the position corresponding to alignment marks made on a bottom wafer. The depth of both cavities is deeper than that of a final membrane structure. The top wafer is then bonded to the bottom wafer which already has alignment marks and a microstructure. This bonded wafer is annealed to intensify its bonding strength. After that, a thinning process is applied until the thickness of the top wafer is reduced to thinner than the cavity depth such that the alignment marks are emerged in the top wafer cavities thereby serving as alignment marks for any exposure equipment.
    Type: Grant
    Filed: November 28, 2003
    Date of Patent: November 22, 2005
    Assignee: Asia Pacific Microsystems, Inc.
    Inventors: Chung-Yang Tseng, Shih-Chin Gong, Reuy-shing Huang, Tong-An Lee, Kuo-Chung Chan, Hung-Dar Wang
  • Patent number: 6864176
    Abstract: A measurement method for the thinned thickness of the silicon wafer, wherein thickness inspection patterns are fabricated onto the silicon wafer substrate by anisotropic etching, and then the wafer is polished with a polisher; thus a wafer with desired thickness can be obtained after the polish is proceeded; the thickness of the upper wafer is determined by the said inspection patterns, then the wafer is sorted by thickness; thus it can be applied to the MEMS micromachined devices that in need of the wafer with such precise thickness.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: March 8, 2005
    Assignee: Asia Pacific Microsystems, Inc.
    Inventors: Hung-Dar Wang, Ruey-Shing Huang, Shih-Chin Gong, Chung-Yang Tseng
  • Publication number: 20050013019
    Abstract: A method of maintaining photolithographic precision alignment for a wafer after being bonded, wherein two cavities are formed at the rear surface of a top wafer at the position corresponding to alignment marks made on a bottom wafer. The depth of both cavities is deeper than that of a final membrane structure. The top wafer is then bonded to the bottom wafer which already has alignment marks and a microstructure. This bonded wafer is annealed to intensify its bonding strength. After that, a thinning process is applied until the thickness of the top wafer is reduced to thinner than the cavity depth such that the alignment marks are emerged in the top wafer cavities thereby serving as alignment marks for any exposure equipment.
    Type: Application
    Filed: November 28, 2003
    Publication date: January 20, 2005
    Inventors: Chung-Yang Tseng, Shih-Chin Gong, Reuy-Shing Huang, Tong-An Lee, Kuo-Chung Chan, Hung-Dar Wang
  • Patent number: 6838303
    Abstract: The present invention relates to a silicon pressure sensor that in need of three strips of piezoresistors on each side and the manufacturing method thereof; wherein, the impurity concentration of the piezoresistors are about 1019-1020 cm?3 in order to reduce the influence of temperature; the lead between the piezoresistors (namely the internal connection lead) is a highly-doping interconnect (about 1021 cm?3) fabricated along the direction with minimum piezoresistance coefficient; with regard to the connection circuit for connecting the piezoresistors with the external Wheatstone bridge circuit (namely the external connection circuit), of which one end near the inner side of the membrane is also fabricated along the direction with minimum piezoresistance coefficient, and another end of the lead near the edge of the membrane is a interconnect that is perpendicular to the diaphragm, and is connected out to the external circuit; with this structure, the four resistors of the Whetstone bridge are balanced and sym
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: January 4, 2005
    Assignee: Asia Pacific Microsystems, Inc.
    Inventors: Hung-Dar Wang, Shih-Chin Gong
  • Publication number: 20040183150
    Abstract: The present invention relates to a silicon pressure sensor that in need of three strips of piezoresistors on each side and the manufacturing method thereof; wherein, the impurity concentration of the piezoresistors are about 1019-1020 cm−3 in order to reduce the influence of temperature; the lead between the piezoresistors (namely the internal connection lead) is a highly-doping interconnect (about 1021 cm−3) fabricated along the direction with minimum piezoresistance coefficient; with regard to the connection circuit for connecting the piezoresistors with the external Wheatstone bridge circuit (namely the external connection circuit), of which one end near the inner side of the membrane is also fabricated along the direction with minimum piezoresistance coefficient, and another end of the lead near the edge of the membrane is a interconnect that is perpendicular to the diaphragm, and is connected out to the external circuit; with this structure, the four resistors of the Whetstone bridge are bala
    Type: Application
    Filed: March 19, 2003
    Publication date: September 23, 2004
    Applicant: Asia Pacific Microsystems, Inc.
    Inventors: Hung-Dar Wang, Shih-Chin Gong
  • Publication number: 20030224610
    Abstract: A measurement method for the thinned thickness of the silicon wafer, wherein thickness inspection patterns are fabricated onto the silicon wafer substrate by anisotropic etching, and then the wafer is polished with a polisher; thus a wafer with desired thickness can be obtained after the polish is proceeded; the thickness of the upper wafer is determined by the said inspection patterns, then the wafer is sorted by thickness; thus it can be applied to the MEMS micromachined devices that in need of the wafer with such precise thickness.
    Type: Application
    Filed: May 28, 2002
    Publication date: December 4, 2003
    Applicant: ASIA PACIFIC MICROSYSTEMS, INC.
    Inventors: Hung-Dar Wang, Ruey-Shing Huang, Shih-Chin Gong, Chung-Yang Tseng