Abstract: A method for manufacturing a panel of a thin film transistor liquid crystal display device with three mask processes is disclosed. The method includes following steps: forming a transparent conductive layer, a first insulating layer, and a second metal layer on a transparent substrate in sequence; forming a source area, a drain area, a transparent electrode area, and data signal lines through a halftone photolithography and an etching; forming a semiconducting layer and a second insulating layer on the substrate in sequence; forming a semiconducting channel area in a thin film transistor area and contacts on the source area, the drain area, and the data signal lines through a photolithography and an etching; forming a third metal layer and a third insulating layer on the substrate in sequence; forming scanning signal lines and gate lines through a photolithography and an etching.

Abstract: A method for manufacturing a thin film transistor array substrate is disclosed. A first metal layer, a gate insulating layer, a semiconductor layer, an ohmic contact layer and a second metal layer are sequentially formed over a substrate, and a first patterning process is carried out to define a source/drain electrodes area, a scan line area, a data line area, a terminal contact area and a pixel area. An interlayer insulating layer is formed, and a second patterning process is implemented to form a source/drain contact hole, a scan line contact hole and a terminal contact hole. A transparent conductive layer, a third metal layer and a passivation layer are sequentially formed over the substrate to achieve electrical contacts among above-mentioned contact holes, and a third patterning process is then implemented to form a thin film transistor, a scan line, a data line, a terminal contact and a pixel electrode.

Abstract: A method for manufacturing a panel of a thin film transistor liquid crystal display device with three mask processes is disclosed. The method includes following steps: forming a transparent conductive layer, a first insulating layer, and a second metal layer on a transparent substrate in sequence; forming a source area, a drain area, a transparent electrode area, and data signal lines through a halftone photolithography and an etching; forming a semiconducting layer and a second insulating layer on the substrate in sequence; forming a semiconducting channel area in a thin film transistor area and contacts on the source area, the drain area, and the data signal lines through a photolithography and an etching; forming a third metal layer and a third insulating layer on the substrate in sequence; forming scanning signal lines and gate lines through a photolithography and an etching.

Abstract: A method for manufacturing a thin film transistor array substrate is disclosed. A first metal layer, a gate insulating layer, a semiconductor layer, an ohmic contact layer and a second metal layer are sequentially formed over a substrate, and a first patterning process is carried out to define a source/drain electrodes area, a scan line area, a data line area, a terminal contact area and a pixel area. An interlayer insulating layer is formed, and a second patterning process is implemented to form a source/drain contact hole, a scan line contact hole and a terminal contact hole. A transparent conductive layer, a third metal layer and a passivation layer are sequentially formed over the substrate to achieve electrical contacts among above-mentioned contact holes, and a third patterning process is then implemented to form a thin film transistor, a scan line, a data line, a terminal contact and a pixel electrode.

Abstract: A method for fabricating a TFT having the steps of providing a substrate; sequentially depositing a transparent conductive layer, a first metal layer, a first insulating layer, a semiconductor layer, and a second metal layer on the substrate; performing a first photo-etching-process (PEP) to remove portions of the deposited layers to form a source electrode and a drain electrode and define a channel region, the first PEP includes a first halftone photolithograph process; depositing a second insulating layer and performing a second PEP to form a plurality of contact holes; and depositing a third metal layer and performing a third PEP to remove portions of the third metal layer.