Abstract: Color image sensors and systems are provided. A color image sensor as disclosed includes a plurality of pixels disposed within an array, each of which includes a plurality of sub-pixels. A pixel array includes pixel cells, each pixel cell including one or more photodiodes. Pixel cells are arranged in rows and columns. The pixel array includes transistors for vertical binning of pixel cells in different rows and transistors for horizontal binning of pixel cells in different columns.

Abstract: In a processing unit, a processor core executes instructions in a plurality of simultaneous hardware threads, where multiple of the plurality of hardware threads concurrently execute memory transactions. A transactional memory circuit in the processing unit tracks transaction footprints of the memory transactions of the multiple hardware thread. In response to detecting failure of a given memory transaction of one of the plurality of multiple threads due to an overflow condition, the transactional memory circuit transitions to a throttled operating mode and reduces a number of hardware threads permitted to concurrently execute memory transactions.

Abstract: In a processing unit, a processor core executes instructions in a plurality of simultaneous hardware threads, where multiple of the plurality of hardware threads concurrently execute memory transactions. A transactional memory circuit in the processing unit tracks transaction footprints of the memory transactions of the multiple hardware thread. In response to detecting failure of a given memory transaction of one of the plurality of multiple threads due to an overflow condition, the transactional memory circuit transitions to a throttled operating mode and reduces a number of hardware threads permitted to concurrently execute memory transactions.