Patents by Inventor Hung-Hao Shen

Hung-Hao Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230153505
    Abstract: Electronic design automation (EDA) of the present disclosure logically places components of the electronic circuitry onto an electronic design real estate to determine an architectural design placement for the electronic circuitry. The EDA evaluates a metaheuristic algorithm starting with an initial placement of components of the electronic circuitry onto the electronic design real estate to provide multiple possible placements for placing these components of the electronic circuitry onto the electronic design real estate. The EDA utilizes the multiple possible placements of the metaheuristic algorithm to train one or more probabilistic functions of a model-based reinforcement learning (RL) algorithm. The EDA evaluates the model-based RL algorithm utilizing the one or more probabilistic functions to determine the architectural design placement.
    Type: Application
    Filed: September 6, 2022
    Publication date: May 18, 2023
    Applicant: MediaTek Inc.
    Inventors: Wei-Hao CHANG, Kai-En YANG, Kao-I CHAO, Yu-Hsun CHEN, Cheng-Feng CHIANG, Yen Min TSAI, Sau Loong LOW, Chia-Shun YEH, Bun Suan HENG, Chia-Yu TSAI, Chin-Tang LAI, Hung-Hao SHEN
  • Publication number: 20220138570
    Abstract: A system performs the operations of a neural network agent and a circuit simulator for analog circuit sizing. The system receives an input indicating a specification of an analog circuit and design parameters. The system iteratively searches a design space until a circuit size is found to satisfy the specification and the design parameters. In each iteration, the neural network agent calculates measurement estimates for random sample generated in a trust region, which is a portion of the design space. Based on the measurement estimate, the system identifies a candidate size that optimizes a value metric. The circuit simulator receives the candidate size and generates a simulation measurement. The system calculates updates to weights of the neural network agent and the trust region for a next iteration based on, at least in part, the simulation measurement.
    Type: Application
    Filed: October 6, 2021
    Publication date: May 5, 2022
    Inventors: Chia-Yu Tsai, Hung-Hao Shen, Chen-Feng Chiang, Chung-An Wang, Yiju Ting, Chia-Shun Yeh, Chin-Tang Lai, Feng-Ming Tsai, Kai-En Yang
  • Patent number: 9215111
    Abstract: A transmission circuit including an equalizer circuit, a slicer circuit, a signal detection circuit, and a control circuit is provided. The equalizer circuit performs an equalizing operation on an input signal according to preset states to output an equalizing signal corresponding to each preset state. The slicer circuit performs a slicing operation on the equalizing signal to output a slicing signal. The signal detection circuit detects and compares the equalizing signal and the slicing signal and accordingly adjusts the equalizer circuit to one of the preset states. The control circuit receives the slicing signal corresponding to each preset state, compares the slicing signal corresponding to each preset state with a plurality of signal patterns to generate a comparison result, and selects one of the preset states according to the comparison result, such that the control circuit let the equalizer circuit perform the equalizing operation according to the selected preset state.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: December 15, 2015
    Assignee: VIA Technologies, Inc.
    Inventors: Hung-Hao Shen, Wei-Yu Wang
  • Publication number: 20140086297
    Abstract: A transmission circuit including an equalizer circuit, a slicer circuit, a signal detection circuit, and a control circuit is provided. The equalizer circuit performs an equalizing operation on an input signal according to preset states to output an equalizing signal corresponding to each preset state. The slicer circuit performs a slicing operation on the equalizing signal to output a slicing signal. The signal detection circuit detects and compares the equalizing signal and the slicing signal and accordingly adjusts the equalizer circuit to one of the preset states. The control circuit receives the slicing signal corresponding to each preset state, compares the slicing signal corresponding to each preset state with a plurality of signal patterns to generate a comparison result, and selects one of the preset states according to the comparison result, such that the control circuit let the equalizer circuit perform the equalizing operation according to the selected preset state.
    Type: Application
    Filed: September 9, 2013
    Publication date: March 27, 2014
    Applicant: VIA Technologies, Inc.
    Inventors: Hung-Hao Shen, Wei-Yu Wang
  • Patent number: 7567112
    Abstract: A voltage level shifter converts an input signal into an output signal. While the input signal is high to the output signal is high either. Moreover, while the input signal is low the output signal is low either.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: July 28, 2009
    Assignee: Via Technologies, Inc.
    Inventor: Hung-Hao Shen
  • Publication number: 20080111609
    Abstract: A voltage level shifter converts an input signal into an output signal. While the input signal is high to the output signal is high either. Moreover, while the input signal is low the output signal is low either.
    Type: Application
    Filed: October 26, 2007
    Publication date: May 15, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: Hung-Hao Shen