Abstract: A method and system are provided for controlling user traffic to a fast packet switching system using the leaky bucket scheme. Each of the packets (53 byte length cell) originates at a source of packets and has a virtual channel identifier (VCI). The method includes the step of receiving the packets, each of the packets having associated therewith an arrival time. The packets are stored at an addressable location in a first memory. The first memory having a plurality of addressable locations. In a second memory, there are stored addresses corresponding to the addressable locations in the first memory in which a packet is not yet stored. The addresses stored in the second memory are utilized in the step of storing the received packets. A credit manager circuit determines whether a stored packet complies with predetermined traffic parameters such as average arrival rate and maximum burst rate. This determination is based on a packet's arrival time and its VCI to obtain a validated packet.

Abstract: A sequencer chip device, provided for use in a broadband integrated service digital network (B-ISDN), is particularly adapted to control users' traffic at two places in the network: at the user-network interface (UNI) by a traffic enforcer, and at the network-node surface interface (NNI) by a queue manager. The traffic enforcer contains a buffer to delay and reshape violating cells that do not comply with some agreed-upon traffic parameters. The queue manager manages cells in a queue at network nodes in such a way that higher priority cells are always served first, low priority cells are discarded when the queue is full, and any interference between same-priority cells is prevented. Proposed architectures for the traffic enforcer and the queue manager include the chip device. The chip device includes a plurality of modules each of which is divided into three main functional areas: controller, memory and comparator. The chip device is preferably implemented using 1.2 .mu.m CMOS technology.

Abstract: A queue management method and system manages queued cells in such a way that higher priority cells are always served first, the low priority cells are dropped when the queue is full and, within the same priority, any interference is prevented. Four different architecture designs for such queue management are presented and their implementation feasibility and hardware complexity are compared and contrasted. A departure sequence is assigned to each cell in the novel architecture to implement the queue management. The sequence applies the concepts of fully distributed and highly parallel processing to schedule cell sending or dropping sequences. Preferably, a sequencer is provided such that the queue size and the number of priority levels can grow flexibly and without limit.

Abstract: To recover the service clock of a variable bit rate source (170) which generates data at a rate which is not proportional to a service clock (76), timing cells are generated. The timing cells are generated at a rate which is proportional to the service clock (76). The timing cells and data are transmitted via a network (100). At the receive-end, the data is stored in a buffer (82). A phase locked loop (90') generates a local clock signal in the form of a read signal which controls the rate at which the received data is read out of the buffer (82). The read signal produced by the phase locked loop (90') is proportional to the average rate at which timing cells are received at the receive-end. In this manner the signal which reads the data out of the buffer (82) at the receive-end approaches the service clock (76) at the source end.

Abstract: Apparatus, and accompanying methods for use therein, for illustratively implementing a large (e.g. approximately 1 Terabit/second) packet switch (200) or a non-buffer based statistical multiplexor (1810), using a crossbar matrix network in which, first, the output ports of individual switching elements (e.g. 1340.sub.1,1, 1340.sub.2,1) are partitioned into various groups (e.g. 1110) in order to share routing paths (links) (e.g. 1115.sub.1, 1115.sub.2, . . . , 1115.sub.K) among the elements in any such group and, second, the outputs of each such group are themselves recursively partitioned into a succession of serially connected groups (e.g. 1140, 1160) that each provides a decreasing number of outputs until one such output is provided for each corresponding output port (278.sub.1, 278.sub.2, . . . , 278.sub.N) of the switch.

Abstract: A crosspoint matrix switching element and associated method for a large (e.g. approximately 1 Terabit/second) packet switch (200) or a non-buffer based statistical multiplexor (1810), using a crossbar matrix network in which, first, the output ports of individual switching elements (e.g. 1340.sub.1,1, 1340.sub.2,1) are partitioned into various groups (e.g. 1110) in order to share routing paths (links) (e.g. 1115.sub.1, 1115.sub.2, . . . , 1115.sub.K) among the elements in any such group and, second, the outputs of each such group are themselves recursively partitioned into a succession of serially connected groups (e.g. 1140, 1160) that each provides a decreasing number of outputs until one such output is provided for each corresponding output port (278.sub.1, 278.sub.2, . . . , 278.sub.N) of the switch.

Abstract: Apparatus, and accompanying methods for use therein, for illustratively implementing a large (e.g. approximately 1 Terabit/second) packet switch (200) or a non-buffer based statistical multiplexor (1810), using a crossbar matrix network in which, first, the output ports of individual switching elements (e.g. 1340.sub.1,1, 1340.sub.2,1) are partitioned into various groups (e.g. 1110) in order to share routing paths (links) (e.g. 1115.sub.1, 1115.sub.2, . . . , 1115.sub.K) among the elements in any such group and, second, the outputs of each such group are themselves recursively partitioned into a succession of serially connected groups (e.g. 1140, 1160) that each provides a decreasing number of outputs until one such output is provided for each corresponding output port (278.sub.1, 278.sub.2, . . . , 278.sub.N) of the switch.

Abstract: A method of controlling the access of a plurality of nodes to a bus which interconnects the nodes in a daisy chain. The method enables each node in the network to keep track of the transmission requests of all other nodes. Each node will compare it's needs against all requests and will only transmit onto the network after it has let pass sufficient resources to satisfy the downstream nodes.

Abstract: A customer premises network for interfacing customer premises equipment with a broadband digital trunk and exchange network comprises a relatively large bandwidth optical broadcast bus for broadcasting downstream data to the customer premises equipment and a smaller bandwidth looped bus for transmitting upstream data from the customer premises equipment. The units of customer premises equipment are connected by the looped bus in a daisy chain.

Abstract: A clock recovery circuit serves to recover a clock signal from data which does not arrive at predetermined times and which may be bursty. The clock recovery circuit operates in conjunction with a buffer which receives the data. Illustratively, the clock recovery circuit maintains a first count of the bytes of data written into the buffer and a second count of the byte of data transferred from the buffer. A subtractor substracts the second count from the first and a decision circuit utilizes the result to provide a signal indicative of the current occupancy of the buffer. Depending on the current occupancy, the frequency of an output signal of the clock recovery circuit is increased, decreased, or maintained as constant. This output signal thus serves as the recovered clock signal.

Abstract: A data transmission technique referred to herein as Dynamic Time Division Multiplexing (DTDM) is disclosed along with a set of multiplexers and demultiplexers required to apply DTDM in an actual telecommunications network. The DTDM technique uses a transmission format which is compatible with the existing digital circuit transmission format and the packet transmission format so that DTDM is able to handle the transmission of circuit and packet traffic. Thus, DTDM provides a flexible migration strategy between present circuit networks and future broadband packet networks.

Abstract: A multiplexer for combining a plurality of relatively sparsely occupied DTDM bit streams into a smaller number of more densely occupied DTDM bit streams at the same bit rate is disclosed. The input lines of the multiplexer are divided into groups so that DTDM frames arriving on the input lines in one group are combined to form one outgoing DTDM bit stream. The outgoing DTDM bit streams are formed by synchronously generating chain of empty frames for each of the input line groups. The frames in a chain are passed to a first member of the appropriate input line group and by means of a cross-point switch to each succeeding member for the insertion of data. The groupings of input lines are defined by the settings of the cross-point switch and may be rearranged by changing the settings of the switch.

Abstract: A multiplexer for time division multiplexing a plurality of DTDM bit streams is disclosed. By taking advantage of the fact that the frames comprising each DTDM bit stream are not 100% occupied, the frequency of the higher speed output bit stream can be made equal to the product of the nominal center frequency of the input tributaries and the number of input tributaries. This is accomplished through the positive and negative stuffing of DTDM frames.

Abstract: A framer circuit which may be implemented as a single chip is disclosed. The framer circuit performs a number of functions in a DTDM network including generating trains of empty DTDM frames, enabling the writing of data packets into specific DTDM frames and the examination of header data in specific DTDM frames to generate signals for the control of peripheral circuits. The framer circuit comprises an input serial/parallel converter, a frame detection circuit, an output parallel/serial converter and a control unit comprising one or more finite state machines for generating proper control signals such as read and write strobes for data insertion and extraction.