Patents by Inventor HUNG-HSIANG KUO
HUNG-HSIANG KUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240186283Abstract: An integrated fan-out (InFO) package includes a die, an encapsulant laterally encapsulating the die, and a redistribution structure. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns and a plurality of alignment marks. The routing patterns are electrically connected to the die. The alignment marks surround the routing patterns. The alignment marks are electrically insulated from the die and the routing patterns. At least one of the alignment marks is in physical contact with the encapsulant, and the alignment marks located at different level heights are arranged in a non-overlapping manner vertically.Type: ApplicationFiled: December 26, 2023Publication date: June 6, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Yung-Chi Chu
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Patent number: 11973023Abstract: A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.Type: GrantFiled: February 3, 2021Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Han Wang, Hung-Jui Kuo, Yu-Hsiang Hu
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Publication number: 20240126174Abstract: A method includes the following steps. A photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a first portion of the photoresist corresponding to a first opaque portion of the first stitching region is unexposed. The photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region, and a second portion of the photoresist corresponding to a second opaque portion of the second stitching region is unexposed and is overlapping with the first portion of the photoresist.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Che Tu, Po-Han Wang, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Package structure comprising buffer layer for reducing thermal stress and method of forming the same
Patent number: 11961777Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.Type: GrantFiled: June 27, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao -
Patent number: 11953740Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.Type: GrantFiled: May 14, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Publication number: 20240113089Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a die, an underfill layer, a patterned dielectric layer and a plurality of conductive terminals. The die has a front surface and a back surface opposite to the front surface. The underfill layer encapsulates the die, wherein a surface of the underfill layer and the back surface of the die are substantially coplanar to one another. The patterned dielectric layer is disposed on the back surface of the die. The conductive terminals are disposed on and in contact with a surface of the patterned dielectric layer and partially embedded in the patterned dielectric layer to be in contact with the die, wherein a portion of the surface of the patterned dielectric layer that directly under each of the conductive terminals is substantially parallel with the back surface of the die.Type: ApplicationFiled: January 10, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tian Hu, Po-Han Wang, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 11948904Abstract: A die includes a substrate, a conductive pad, a connector and a protection layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector includes a seed layer and a conductive post. The protection layer laterally covers the connector. Topmost surfaces of the seed layer and the conductive post and a top surface of the protection layer are level with each other.Type: GrantFiled: March 21, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
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Patent number: 11948863Abstract: A package structure and method of forming the same are provided. The package structure includes a polymer layer, a redistribution layer, a die, and an adhesion promoter layer. The redistribution layer is disposed over the polymer layer. The die is sandwiched between the polymer layer and the redistribution layer. The adhesion promoter layer, an oxide layer, a through via, and an encapsulant are sandwiched between the polymer layer and the redistribution layer. The encapsulant is laterally encapsulates the die. The through via extends through the encapsulant. The adhesion promoter layer and the oxide layer are laterally sandwiched between the through via and the encapsulant. A bottom portion of the encapsulant is longitudinally sandwiched between the adhesion promoter layer and the polymer layer.Type: GrantFiled: February 8, 2023Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Wei-Chih Chen
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Patent number: 11947173Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: GrantFiled: May 5, 2023Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 11948918Abstract: A semiconductor device having a redistribution structure and a method of forming the same are provided. A semiconductor device includes a semiconductor structure, a redistribution structure over and electrically coupled the semiconductor structure, and a connector over and electrically coupled to the redistribution structure. The redistribution structure includes a base via and stacked vias electrically interposed between the base via and the connector. The stacked vias are laterally spaced apart from the base via.Type: GrantFiled: November 17, 2020Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 11942435Abstract: In an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated circuit die; and a redistribution structure over the integrated circuit die, the molding compound, and the through via, the redistribution structure electrically connected to the integrated circuit die and the through via, the redistribution structure including: a first dielectric layer disposed over the molding compound; a first conductive via extending through the first dielectric layer; a second dielectric layer disposed over the first dielectric layer and the first conductive via; and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, an interface between the first conductive via and the second conductive via being non-planar.Type: GrantFiled: April 18, 2023Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Han Wang, Hung-Jui Kuo, Yu-Hsiang Hu
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Patent number: 11942417Abstract: A device includes a sensor die having a sensing region at a top surface of the sensor die, an encapsulant at least laterally encapsulating the sensor die, a conductive via extending through the encapsulant, and a front-side redistribution structure on the encapsulant and on the top surface of the sensor die, wherein the front-side redistribution structure is connected to the conductive via and the sensor die, wherein an opening in the front-side redistribution structure exposes the sensing region of the sensor die, and wherein the front-side redistribution structure includes a first dielectric layer extending over the encapsulant and the top surface of the sensor die, a metallization pattern on the first dielectric layer, and a second dielectric layer extending over the metallization pattern and the first dielectric layer.Type: GrantFiled: May 4, 2020Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yung-Chi Chu, Sih-Hao Liao, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
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Publication number: 20240088056Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Inventors: Jhih-Yu Wang, Yung-Chi Chu, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 11923207Abstract: A method for forming a redistribution structure in a semiconductor package and a semiconductor package including the redistribution structure are disclosed. In an embodiment, the method may include encapsulating an integrated circuit die and a through via in a molding compound, the integrated circuit die having a die connector; depositing a first dielectric layer over the molding compound; patterning a first opening through the first dielectric layer exposing the die connector of the integrated circuit die; planarizing the first dielectric layer; depositing a first seed layer over the first dielectric layer and in the first opening; and plating a first conductive via extending through the first dielectric layer on the first seed layer.Type: GrantFiled: April 28, 2023Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
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Publication number: 20240069277Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Kuo, Chen-Hua Yu, Cheng-Chieh Hsieh, Che-Hsiang Hsu, Chung-Ming Weng, Tsung-Yuan Yu
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Publication number: 20220314399Abstract: Some embodiments of the present application disclose a polishing liquid supply system. In the present application, the polishing liquid supply system includes: a polishing liquid preparation device, a cleaning liquid supply device and a filtering device, and further includes a supply pipeline connected with the polishing liquid preparation device and the filtering device and a cleaning pipeline connected with the cleaning liquid supply device and the filtering device. The polishing liquid preparation device is configured to prepare a polishing liquid and convey the prepared polishing liquid to the filtering device through the supply pipeline. The filtering device is configured to filter the polishing liquid and convey the filtered polishing liquid to a polishing device connected with the filtering device. The cleaning liquid supply device is configured to convey a cleaning liquid to the filtering device through the cleaning pipeline.Type: ApplicationFiled: February 9, 2021Publication date: October 6, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Fuyou JIANG, HUNG-HSIANG KUO, Chin-Chung KU