Abstract: A redistribution structure is made using filler-free insulating materials with high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.

Abstract: An image sensor includes a sensor layer and a color filter layer disposed on the sensor layer. The image sensor further includes a lens layer disposed on the color filter layer. The lens layer includes a plurality of micro lenses. The image sensor further includes a first cut filter layer disposed over the lens layer. The first surface of the first cut filter layer has a plurality of first protrusions.

Abstract: In an embodiment, a method includes forming a conductive feature adjacent to a substrate; treating the conductive feature with a protective material, the protective material comprising an inorganic core with an organic coating around the inorganic core, the treating the conductive feature comprising forming a protective layer over the conductive feature; and forming an encapsulant around the conductive feature and the protective layer. In another embodiment, the method further includes, before forming the encapsulant, rinsing the protective layer with water. In another embodiment, the protective layer is selectively formed over the conductive feature.

Abstract: A fan-out package includes a molding compound die frame laterally surrounding at least one semiconductor die; and an organic interposer including redistribution dielectric layers embedding redistribution wiring interconnects and located on a first horizontal surface of the molding compound die frame. An alignment mark region including a localized recess region is located within an opening in a second horizontal surface of the molding compound die frame. The localized recess region extends from the second horizontal surface toward the organic interposer.

Abstract: An apparatus and a method for effectively exhausting evaporated material are provided. In an embodiment the apparatus includes a hot plate and an exhaust hood assembly suspended over the hot plate. The exhaust hood assembly includes a trench plate, a cover plate over the trench plate and a single exhaust pipe header over and attached to a single exhaust opening of the cover plate. During operation, the exhaust hood assembly reduces the amount of condensation and also collects any remaining condensation in order to help prevent condensation from impacting further manufacturing steps.

Abstract: A method of fabricating a redistribution circuit structure including the following steps is provided. A conductive via is formed. A photosensitive dielectric layer is formed to cover the conductive via. The photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. A redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via.

Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.

Abstract: A package including a device die and an encapsulant is provided. The device die includes a semiconductor substrate, an interconnect structure, a conductive via, and a dielectric layer. The interconnect structure is disposed over the semiconductor substrate. The conductive via is disposed over and electrically coupled to the interconnect structure. The dielectric layer is disposed over the interconnect structure and laterally encapsulating the conductive via, wherein the dielectric layer includes a sidewall and a bottom surface facing the interconnect structure, and the sidewall of the dielectric layer is tilted with respect to the bottom surface of the dielectric layer. The encapsulant laterally encapsulates the device die.

Abstract: A package includes an electronic die, a photonic die underlying and electronically communicating with the electronic die, a lens disposed on the electronic die, and a prism structure disposed on the lens and optically coupled to the photonic die. The prism structure includes first and second polymer layers, the first polymer layer includes a first curved surface concaving toward the photonic die, the second polymer layer embedded in the first polymer layer includes a second curved surface substantially conforming to the first curved surface, and an outer sidewall of the second polymer layer substantially aligned with an outer sidewall of the first polymer layer.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor dies, a dielectric layer, a connector, and a passivation layer. The plurality of semiconductor dies are stacked on one another and disposed over the semiconductor substrate. The dielectric layer cover a top surface and a side surface of the each of the plurality of semiconductor dies. The connector is disposed over a topmost one of the plurality of semiconductor dies. The passivation layer is disposed over the dielectric layer and laterally surrounds the connector, wherein, from a cross sectional view, an acute angle is included between an outermost side surface of the passivation layer and a bottom surface of the passivation layer.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.

Abstract: A method includes forming a metal post over a first redistribution structure; attaching a first device die to the first redistribution structure, the first device die comprising a through via embedded in a semiconductor substrate; encapsulating the metal post and the first device die in an encapsulant, a first top surface of the encapsulant being level with a second top surface of the semiconductor substrate; recessing the second top surface to expose the through via; forming a dielectric isolation layer around the through via; forming a dielectric layer over the dielectric isolation layer; etching the dielectric layer to form a first opening and a second opening in the dielectric layer; forming a first metal via in the first opening and a second metal via in the second opening; and forming a second redistribution structure over the dielectric layer.

Abstract: A package structure includes a plurality of semiconductor die, an insulating encapsulant and a redistribution layer. Each of the plurality of semiconductor dies includes a semiconductor substrate, conductive pads disposed on the semiconductor substrate, conductive posts disposed on the conductive pads, and at least one alignment mark located on the semiconductor substrate. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the plurality of semiconductor dies.

Abstract: A chip package includes a semiconductor die laterally encapsulating by an insulating encapsulant, a first dielectric portion, conductive vias, conductive traces and a second dielectric portion. The first dielectric portion covers the semiconductor die and the encapsulant. The conductive vias penetrate through the first dielectric portion and electrically connected to the semiconductor die. The conductive traces are disposed on the first dielectric portion. The second dielectric portion is disposed on the first dielectric portion and covering the conductive traces, wherein a first minimum lateral width of a conductive trace among the conductive traces is smaller than a second minimum lateral width of a conductive via among the conductive vias. A method of forming the chip package is also provided.

Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.

Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.

Abstract: A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.

Abstract: Some embodiments of the present application disclose a polishing liquid supply system. In the present application, the polishing liquid supply system includes: a polishing liquid preparation device, a cleaning liquid supply device and a filtering device, and further includes a supply pipeline connected with the polishing liquid preparation device and the filtering device and a cleaning pipeline connected with the cleaning liquid supply device and the filtering device. The polishing liquid preparation device is configured to prepare a polishing liquid and convey the prepared polishing liquid to the filtering device through the supply pipeline. The filtering device is configured to filter the polishing liquid and convey the filtered polishing liquid to a polishing device connected with the filtering device. The cleaning liquid supply device is configured to convey a cleaning liquid to the filtering device through the cleaning pipeline.

Abstract: Some embodiments of the present application disclose a polishing liquid supply system. In the present application, the polishing liquid supply system includes: a polishing liquid preparation device, a cleaning liquid supply device and a filtering device, and further includes a supply pipeline connected with the polishing liquid preparation device and the filtering device and a cleaning pipeline connected with the cleaning liquid supply device and the filtering device. The polishing liquid preparation device is configured to prepare a polishing liquid and convey the prepared polishing liquid to the filtering device through the supply pipeline. The filtering device is configured to filter the polishing liquid and convey the filtered polishing liquid to a polishing device connected with the filtering device. The cleaning liquid supply device is configured to convey a cleaning liquid to the filtering device through the cleaning pipeline.