Patents by Inventor Hung-Hsiang Lin

Hung-Hsiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230018511
    Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.
    Type: Application
    Filed: July 16, 2021
    Publication date: January 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
  • Patent number: 11555531
    Abstract: A cycloid speed reducer includes an input shaft, a rolling assembly, first and second cycloid discs, a crankshaft and an output disc. The first and second cycloid discs are disposed around the input shaft and driven by the input shaft. The first and second cycloid discs are located at two opposite sides of the rolling assembly, respectively. The crankshaft includes first and second eccentric ends and first and second concentric ends integrally formed as a one-piece structure and arranged sequentially. The first and second eccentric ends are linked with the first and second cycloid discs respectively. An eccentricity value is between any neighboring two of the concentric and eccentric ends. The diameters of all the concentric and eccentric ends are equal. The output disc is linked with the first or second concentric end. The output disc is a power output end of the cycloid speed reducer.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: January 17, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chi-Wen Chung, Hung-Wei Lin, Wei-Ying Chu, Chin-Hsiang Chen
  • Publication number: 20230009477
    Abstract: A machine and a wafer processing apparatus are provided; the machine includes a body and an adjustment part. The body is configured to bear a wafer; the adjustment part is disposed in the body, and the adjustment part uses a vacuum suction to adjust a levelness of an in-process wafer.
    Type: Application
    Filed: October 19, 2021
    Publication date: January 12, 2023
    Inventor: HUNG-HSIANG LIN
  • Patent number: 11545427
    Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: January 3, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Chien-Hua Chen, Teck-Chong Lee, Hung-Yi Lin, Pao-Nan Lee, Hsin Hsiang Wang, Min-Tzu Hsu, Po-Hao Chen
  • Patent number: 11539625
    Abstract: A packet processing system including an ingress unit, a detour launcher, a packet sequencer, a post-detour handler and an egress unit. The ingress unit is used to receive a packet. The detour launcher is used to detect a microburst according to at least a queue value and accordingly send the packet. The packet sequencer is used to attach a sequence number to the packet when the microburst emerges. The post-detoured handler is used to release the packet after the microburst has elapsed. The egress unit is used to output the packet processed by at least one member of a group consisting of the detour launcher, the packet sequencer and the post-detour handler.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: December 27, 2022
    Assignees: Inventec (Pudong) Technology Corp., Inventec Corporation
    Inventors: Po-Jen Chen, Yu-Chieh Lin, Hung-Pin Wen, Chi-Hsiang Hung
  • Publication number: 20220382004
    Abstract: An optical interconnect structure including a base substrate, an optical waveguide, a first reflector, a second reflector, a dielectric layer, a first lens, and a second lens is provided. The optical waveguide is embedded in the base substrate. The optical waveguide includes a first end portion and a second end portion opposite to the first end portion. The first reflector is disposed between the base substrate and the first end portion of the optical waveguide. The second reflector is disposed between the base substrate and the second end portion of the optical waveguide. The dielectric layer covers the base substrate and the optical waveguide. The first lens is disposed on the dielectric layer and located above the first end portion of the optical waveguide. The second lens is disposed on the dielectric layer and located above the second end portion of the optical waveguide.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Yu-Hsiang Hu, Chewn-Pu Jou, Feng-Wei Kuo
  • Publication number: 20220375729
    Abstract: An edge ring, for a plasma etcher, may include a circular bottom portion with an opening sized to receive an electrostatic chuck supporting a semiconductor device, and a circular top portion integrally connected to a first top part of the circular bottom portion. The edge ring may include a circular chamfer portion integrally connected to a second top part of the circular bottom portion and integrally connected to a side of the circular top portion. The circular chamfer portion may include an inner surface that is angled radially outward from the opening at less than ninety degrees.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Inventors: Chien-Yu WANG, Hung-Bin LIN, Shih-Ping HONG, Shih-Hao CHEN, Chen-Hsiang LU, Ping-Chung LEE
  • Patent number: 11508585
    Abstract: A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Liang-Guang Chen, Kei-Wei Chen, Hung Yen, Ting-Hsun Chang, Chi-Hsiang Shen, Li-Chieh Wu, Chi-Jen Liu
  • Publication number: 20220367266
    Abstract: A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.
    Type: Application
    Filed: July 21, 2021
    Publication date: November 17, 2022
    Inventors: Shu-Cheng Chin, Chih-Yi Chang, Wei Hsiang Chan, Chih-Chien Chi, Chi-Feng Lin, Hung-Wen Su
  • Publication number: 20220365273
    Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.
    Type: Application
    Filed: May 13, 2021
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
  • Publication number: 20220365297
    Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Publication number: 20220320104
    Abstract: A method for forming a memory includes: providing a substrate, a plurality of discrete bit line structures being located on the substrate, and an area surrounded by the adjacent bit line structures and the substrate and having a central axis; forming, on the substrate, a first conductive film filling an area between the adjacent bit line structures; etching the first conductive film by a first etching process to form a first conductive layer; forming a second conductive film on the top surface of the first conductive layer; and etching the second conductive film and the first conductive layer by a second etching process, the remaining second conductive film and the first conductive layer forming a capacitive contact window.
    Type: Application
    Filed: April 1, 2021
    Publication date: October 6, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xiao ZHU, YI-HSIANG CHEN, Lihui YANG, HUNG-I LIN, Yun-Chieh MI, Jinfeng GONG
  • Publication number: 20220299719
    Abstract: A photonic integrated circuit includes a substrate, an interconnection layer, and a plurality of silicon waveguides. The interconnection layer is over the substrate. The interconnection layer includes a seal ring structure and an interconnection structure surrounded by the seal ring structure. The seal ring structure has at least one recess from a top view. The recess concaves towards the interconnection structure. The silicon waveguides are embedded in the substrate.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Ming Weng, Hua-Kuei Lin, Che-Hsiang Hsu
  • Publication number: 20220293528
    Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.
    Type: Application
    Filed: April 28, 2021
    Publication date: September 15, 2022
    Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su
  • Publication number: 20220283641
    Abstract: In one example, an electronic device may include a touch panel defining an input surface having an input region and a display panel disposed below the touch panel. The display panel may visualize a virtual keyboard including a set of virtual keys. Further, the electronic device may include a haptic array module disposed below the display panel. The haptic array module may include a first actuator disposed below the input region corresponding to a first virtual key of the set of virtual keys. Further, the electronic device may include a controller in communication with the haptic array module to trigger the first actuator to generate a haptic output at the input region in response to an activation of the virtual keyboard.
    Type: Application
    Filed: November 8, 2019
    Publication date: September 8, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Hung-Ming Chen, Charles Stancil, Tai Hsiang Chen, Wei Hung Lin
  • Publication number: 20220246435
    Abstract: A method of manufacturing a semiconductor structure includes receiving a die comprising a top surface and a sacrificial layer covering the top surface; disposing a molding surrounding the die; removing the sacrificial layer from the die; disposing a polymer over the die and the molding, wherein the polymer has a first bottom surface contacting the die and a second bottom surface contacting the molding, and the first bottom surface is at a level substantially same as the second bottom surface.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Inventors: YU-HSIANG HU, WEI-YU CHEN, HUNG-JUI KUO, WEI-HUNG LIN, MING-DA CHENG, CHUNG-SHI LIU
  • Patent number: 11404250
    Abstract: An edge ring, for a plasma etcher, may include a circular bottom portion with an opening sized to receive an electrostatic chuck supporting a semiconductor device, and a circular top portion integrally connected to a first top part of the circular bottom portion. The edge ring may include a circular chamfer portion integrally connected to a second top part of the circular bottom portion and integrally connected to a side of the circular top portion. The circular chamfer portion may include an inner surface that is angled radially outward from the opening at less than ninety degrees.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yu Wang, Hung-Bin Lin, Shih-Ping Hong, Shih-Hao Chen, Chen-Hsiang Lu, Ping-Chung Lee
  • Publication number: 20220229494
    Abstract: Techniques for proving haptic feedback in computing systems are described. In operation, an input representing utilisation parameters of an electronic pen is received. In an example, the electronic pen may be electronically coupled to the computing system. Based on the received utilisation parameters, the computing system provides a pattern of haptic feedback to the user.
    Type: Application
    Filed: September 16, 2019
    Publication date: July 21, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Charles J. Stancil, Tai Hsiang Chen, Hung-Ming Chen, Simon Wong, Hsiang-Ta Ke, Yi-Hsien Lin, Jung-Hsing Wang
  • Patent number: 11373956
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first semiconductor device, a first conductive layer and a second conductive layer. The first semiconductor device has a first conductive pad. The first conductive layer is disposed in direct contact with the first conductive pad. The first conductive layer extends along a direction substantially parallel to a surface of the first conductive pad. The second conductive layer is disposed in direct contact with the first conductive pad and spaced apart from the first conductive layer.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: June 28, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Min Lung Huang, Hung-Jung Tu, Hsin Hsiang Wang, Chih-Wei Huang, Shiuan-Yu Lin
  • Publication number: 20210046667
    Abstract: A liquid collection device is adapted for collecting liquid flowing along a flow path. The liquid collection device includes a collection unit including a top wall member, a bottom wall member, and a surrounding wall member. The top wall member has a liquid inlet extending along the flow path through the top wall member. The bottom wall member is disposed downstream of the top wall member. The surrounding wall member extends from a perimeter of the bottom wall member toward the top wall member. The top wall member covers the surrounding wall member, and cooperates with the bottom wall member and the surrounding wall member to define a liquid-holding space therein, the liquid inlet being spatially communicated to the liquid-holding space.
    Type: Application
    Filed: September 30, 2019
    Publication date: February 18, 2021
    Inventors: Yo-Hsin SU, Chia-Hao Liu, Hung-Hsiang Lin