Abstract: A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.

Abstract: A method includes the following steps. A photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a first portion of the photoresist corresponding to a first opaque portion of the first stitching region is unexposed. The photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region, and a second portion of the photoresist corresponding to a second opaque portion of the second stitching region is unexposed and is overlapping with the first portion of the photoresist.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a die, an underfill layer, a patterned dielectric layer and a plurality of conductive terminals. The die has a front surface and a back surface opposite to the front surface. The underfill layer encapsulates the die, wherein a surface of the underfill layer and the back surface of the die are substantially coplanar to one another. The patterned dielectric layer is disposed on the back surface of the die. The conductive terminals are disposed on and in contact with a surface of the patterned dielectric layer and partially embedded in the patterned dielectric layer to be in contact with the die, wherein a portion of the surface of the patterned dielectric layer that directly under each of the conductive terminals is substantially parallel with the back surface of the die.

Abstract: A semiconductor device having a redistribution structure and a method of forming the same are provided. A semiconductor device includes a semiconductor structure, a redistribution structure over and electrically coupled the semiconductor structure, and a connector over and electrically coupled to the redistribution structure. The redistribution structure includes a base via and stacked vias electrically interposed between the base via and the connector. The stacked vias are laterally spaced apart from the base via.

Abstract: In an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated circuit die; and a redistribution structure over the integrated circuit die, the molding compound, and the through via, the redistribution structure electrically connected to the integrated circuit die and the through via, the redistribution structure including: a first dielectric layer disposed over the molding compound; a first conductive via extending through the first dielectric layer; a second dielectric layer disposed over the first dielectric layer and the first conductive via; and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, an interface between the first conductive via and the second conductive via being non-planar.

Abstract: A device includes a sensor die having a sensing region at a top surface of the sensor die, an encapsulant at least laterally encapsulating the sensor die, a conductive via extending through the encapsulant, and a front-side redistribution structure on the encapsulant and on the top surface of the sensor die, wherein the front-side redistribution structure is connected to the conductive via and the sensor die, wherein an opening in the front-side redistribution structure exposes the sensing region of the sensor die, and wherein the front-side redistribution structure includes a first dielectric layer extending over the encapsulant and the top surface of the sensor die, a metallization pattern on the first dielectric layer, and a second dielectric layer extending over the metallization pattern and the first dielectric layer.

Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.

Abstract: A random bit cell includes a latch and a nonvolatile memory cell. The nonvolatile memory cell includes a storage circuit, a control element, an erase element, and a read circuit. The storage circuit is coupled to a first terminal of the latch. The storage circuit includes a floating gate transistor having a first terminal, a second terminal, and a floating gate. The control element has a first terminal coupled to a control line, and a control terminal coupled to the floating gate of the floating gate transistor. The erase element has a first terminal coupled to an erase line, and a control terminal coupled to the floating gate of the floating gate transistor. The read circuit is coupled to a bit line, a select gate line, and the floating gate of the floating gate transistor.

Abstract: A random bit cell includes a latch and a nonvolatile memory cell. The nonvolatile memory cell includes a storage circuit, a control element, an erase element, and a read circuit. The storage circuit is coupled to a first terminal of the latch. The storage circuit includes a floating gate transistor having a first terminal, a second terminal, and a floating gate. The control element has a first terminal coupled to a control line, and a control terminal coupled to the floating gate of the floating gate transistor. The erase element has a first terminal coupled to an erase line, and a control terminal coupled to the floating gate of the floating gate transistor. The read circuit is coupled to a bit line, a select gate line, and the floating gate of the floating gate transistor.

Abstract: The disclosure is directed to a method of controlling a heterogeneous network and related apparatuses using the same method. In one of the exemplary embodiments, the disclosure is directed to a method controlling a heterogeneous network applicable to a base station, the method includes not limited to: transmitting a first configuration message comprising a measurement and report rule (MRR) which comprises a first measuring interval, a second measuring interval, a first reporting interval, and a second reporting interval for receiving a measurement report of a channel of an unlicensed spectrum; receiving the measurement report of the channel of the unlicensed spectrum after transmitting the first configuration message; and transmitting a second configuration message to update the MRR.

Abstract: The disclosure is directed to a method of controlling a heterogeneous network and related apparatuses using the same method. In one of the exemplary embodiments, the disclosure is directed to a method controlling a heterogeneous network applicable to a base station, the method includes not limited to: transmitting a first configuration message comprising a measurement and report rule (MRR) which comprises a first measuring interval, a second measuring interval, a first reporting interval, and a second reporting interval for receiving a measurement report of a channel of an unlicensed spectrum; receiving the measurement report of the channel of the unlicensed spectrum after transmitting the first configuration message; and transmitting a second configuration message to update the MRR.

Abstract: An unlicensed carrier evaluating method and an evolved Node B (eNB) using the same are provided. The unlicensed carrier evaluating method includes the following steps. An eNB transmits a configuration information to at least one user equipment (UE). The configuration information includes a timing parameter. The at least one UE transmits at least one preamble sequence to a Licensed Assisted Access (LAA) node through at least one unlicensed carrier according to the configuration information. The LAA node is connected to the eNB. The eNB or the LAA node evaluates a transmission efficiency of the at least one unlicensed carrier according to the at least one preamble sequence.

Abstract: A dynamic encryption type fingerprint sensor includes a capacitive array sensing fingerprints and producing fingerprint data, an embedded non-volatile memory (eNVM) storing a one-time code (OTC) and an encryption algorithm indicator, and a logic algorithm circuit encrypting the fingerprint data produced by the capacitive array according to the OTC and the encryption algorithm indicator. The logic algorithm circuit includes an encryption circuit having a plurality of logic encryption circuits selected using the encryption algorithm indicator, the encryption circuit encrypting the fingerprint data using selected logic encryption circuits of the plurality of logic encryption circuits according to the OTC. A control circuit is used for controlling operation of the capacitive array, the eNVM, and the logic algorithm circuit.

Abstract: A method for controlling a distributed antenna system includes the following steps. A target propagation delay value is defined according to a transmit/receive transition gap. Propagation delay time of a service antenna unit corresponding to a base station is estimated. The service antenna unit is turned on to perform downlink signal transmission, and the propagation delay time of the service antenna unit is compensated to the target propagation delay value.

Abstract: A transmitter and an identification pattern transmission method thereof and a receiver and an identification pattern detection method thereof are provided. The transmitter includes a random sequence generator, a mapper and a resource allocation unit. The identification pattern transmission method includes following steps. A random sequence is generated. The random sequence is mapped to an identification pattern. The identification pattern is partitioned into a plurality of identification segments. The identification segments are allocated to a plurality of communication resource blocks to generate a transmitted signal having information of the identification pattern, where each of the communication resource blocks is spaced from another adjacent communication resource block by a predetermined number of symbols and/or a predetermined number of subcarriers.

Abstract: A symbol timing method for a multi-carrier system is provided, including: receiving an input symbol; executing a correlation operation by using a first summation window with a size smaller than a duplicated data to generate a first characteristic signal; determining a first search region according to a first predetermined threshold and the first characteristic signal and searching a local peak value in the first search region; locating a right edge point of the first characteristic signal according to a difference value and the local peak value; obtaining a coarse symbol timing position for a following input symbol according to a predetermined movement and the right edge point; and outputting the coarse symbol timing position to a signal transformation module, wherein signal transformation is executed by the signal transformation module according to the coarse symbol timing position.

Abstract: A method for controlling a distributed antenna system includes the following steps. A target propagation delay value is defined according to a transmit/receive transition gap. Propagation delay time of a service antenna unit corresponding to a base station is estimated. The service antenna unit is turned on to perform downlink signal transmission, and the propagation delay time of the service antenna unit is compensated to the target propagation delay value.

Abstract: A system and method corrects erroneous sections received in a memory by pre-filling at least a portion of memory with a pre-defined value. If a received data packet is valid, the valid received data packet is stored over the pre-defined values in the memory location associated with the valid data packet. Values associated with a data segment and an adjacent data segment in the memory are compared to the pre-defined value. When the values of each data segment match the pre-defined values, then each data segment is an erroneous data segment.