Abstract: The disclosure provides an electrical apparatus. The electrical apparatus includes a timing controller, a data driver circuit, and a display panel. The timing controller is configured to receive at least one data polarity configuration signal. The timing controller generates and outputs a plurality of polarity inversion signals according to the data polarity configuration signal. The phases of the polarity inversion signals are different. The data driver circuit is coupled to the timing controller. The data driver circuit is configured to receive the polarity inversion signals. The display panel is coupled to the data driver circuit. The display panel is configured to display images. The data driver circuit drives the display panel to display the images according to the polarity inversion signals.

Abstract: An example display for a computing device includes: a display layer; a dynamic liquid crystal antenna formed substantially parallel to the display layer, the dynamic liquid crystal antenna comprising: a liquid crystal layer; a pixelated driving electrode to selectively activate pixels of the liquid crystal layer to form an antenna structure; and a common electrode extending between the liquid crystal layer and the display layer to isolate the liquid crystal layer from the display layer.

Abstract: A semiconductor device includes a substrate and at least one functional layer. The functional layer includes: a first signal line layer and a second signal line layer, stacked on the substrate in a vertical direction, the first signal line and the second signal line each extends in a first horizontal direction; and each has a body extension portion and a lead-out end, and for each of the first signal line and the second signal line, the lead-out end is located at least one end of the body extension portion; orthographic projection of the body extension portion of the first signal line and the second signal line on the substrate are overlapping; and orthographic projections of the lead-out ends of the first signal line and the second signal line on the substrate are non-overlapping. This solution facilitates the independent lead-out of signal lines from each layer.

Abstract: An electronic device includes a first buffer, a second buffer, and a multiplexer. The first buffer receives and stores first data when the first buffer is not full, and performs a First-In-First-Out (FIFO) operation on the first data. The second buffer receives and stores second data when the first buffer is full, and performs the FIFO operation on the second data. The multiplexer is electrically connected between the first buffer and the second buffer. The multiplexer receives the first data from outside of the electronic device, or it receives the second data from the second buffer. A depth of the first buffer is less than that of the second buffer.

Abstract: A method for enhancing an expression of insulin like growth factor 1 receptor in an umbilical cord mesenchymal stem cell is provided. The method includes culturing the umbilical cord mesenchymal stem cell expressing insulin-like growth factor 1 receptor in a medium containing platelet-derived growth factor BB (PDGF-BB) to enhance the expression of insulin like growth factor 1 receptor in the umbilical cord mesenchymal stem cell.

Abstract: The present disclosure provides a semiconductor device structure with conductive contact of different widths and a method for preparing the semiconductor device structure. The semiconductor device structure includes a dielectric layer disposed over a semiconductor substrate, and a first conductive contact penetrating through the dielectric layer. The first conductive contact includes a first metal filling layer and a first metal silicide structure surrounding the first metal filling layer. The semiconductor device structure also includes a second conductive contact penetrating through the dielectric layer. The second conductive contact includes a second metal filling layer and a second metal silicide structure surrounding the second metal filling layer, and a first width of the first conductive contact is different from a second width of the second conductive contact.

Abstract: A bond structure is provided. The bond structure includes a seed layer and a conductive structure. The conductive structure includes a via portion over the seed layer and a plurality of wires protruding from the via portion.

Abstract: A light emitting device and a light source module are provided. The light emitting device includes a base, a conductive unit, a light unit, and a package. The base includes a first substrate and n through holes, and the through holes pass through the first substrate. The conductive unit includes m conductors that are separate from each other, and the conductors pass through the first substrate. The light unit is electrically connected to the conductors. The package includes a first package body surrounding the light unit and a second package body covering the light unit and the first package body. The first package body and the second package body have different optical properties. Furthermore, m and n are integers greater than or equal to 2, and m is greater than or equal to n.

Abstract: An optical imaging lens adapted to limited working distance is disclosed. The optical imaging lens includes a first, a second, a third, a fourth, a fifth, a sixth lens elements and an image sensing element sequentially along an optical axis from an object-side to an image-side. The first to the sixth lens element each includes an object-side surface facing toward an object-side as well as an image-side surface facing toward an image-side. The first lens element is a wide-angle lens element. The second to the sixth lens element are a combination of aspherical lens element, molded glass lens element, and free-form surface lens element. A field of view of the optical imaging lens is greater than or equal to 100 degrees, and the optical imaging lens is a wide-angle lens.

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: An anomaly detection device based on a generative adversarial network architecture, which uses the single-type training data composed of multiple normal signals to train an anomaly detection model. The anomaly detection device includes an encoder, a generator, a discriminator, and a random vector generator. In the training phase of anomaly detection model, the random latent vectors generated by the random vector generator are sequentially input to a generator to generate the synthesized signals with the same dimension as the normal signals. The synthesized signals are sequentially input into a discriminator to output the corresponding discriminant values. When the corresponding discriminant values are under the predetermined threshold, the corresponding synthesized signals are selected as the anomalous class training data, and the real normal signals are selected as the normal class training data.

Abstract: A display device includes an aperture layer, a first plurality of light sources, a second plurality of light sources, and a piezo material coupled to the first plurality of light sources and the second plurality of light sources. The aperture layer includes a first plurality of apertures and a second plurality of apertures, and the first plurality of light sources is arranged to correspond to the first plurality of apertures, and the second plurality of light sources is arranged to correspond to the second plurality of apertures. The piezo material is configured to alter a first position of the first plurality of light sources relative to the first plurality of apertures, and to alter a second position of the second plurality of light sources relative to the second plurality of apertures.

Abstract: An optical semiconductor device with cascade vias is disclosed. The semiconductor device a logic die having a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and having a memory cell area and a memory peripheral area; a first inter-die via positioned in the memory peripheral area; a landing pad positioned on the first inter-die via; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area. The first inter-die via and the first intra-die via are electrically coupled through the landing pad in a cascade manner.

Abstract: In some examples, a computing device can include a memory resource storing instructions to cause a processor resource to receive, from a first virtual machine assigned a first color gamut, display characteristics of a first display, display characteristics of a second display, or both. In some examples, the instructions can cause the processor resource to receive, from a second virtual machine assigned a second color gamut, the display characteristics of the first display, the display characteristics of the second display, or both, and determine, based on the first color gamut, the second color gamut, and the display characteristics, a color gamut mapping for the first color gamut and the second color gamut. In some examples, the instructions can cause the processor resource to map the first color gamut to the first display and map the second color gamut to the second display based on the color gamut mapping.

Abstract: A force touch judgement method is applied to a force touch pad with two force sensors. Firstly, a force touch operation corresponding to a real force value is performed on a force touch position. Then, a first sensing signal value and a second sensing signal value corresponding to the force touch operation are respectively generated by the two force sensors. Then, the first sensing signal value and the second sensing signal value are added as a total sensing signal value. A calibration force value corresponding to the force touch position is obtained. A first calibration signal value and a second calibration signal value corresponding to the force touch position are added as a total calibration signal value. A ratio of the total sensing signal value to the total calibration signal value is equal to a ratio of the real force value to the calibration force value.

Abstract: An integrated circuit includes a first substrate having a first substrate material, and the first substrate includes a first circuit. A second substrate has a second substrate material different than the first substrate material, and the second substrate includes a second circuit. A conductive interconnect electrically connects the first circuit and the second circuit.

Abstract: The present application discloses a semiconductor device with a barrier layer including aluminum fluoride and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a circuit layer positioned on the substrate, a pad layer positioned in the circuit layer and including aluminum and copper, a first barrier layer positioned on the pad layer and including aluminum fluoride, and a first connector positioned on the first barrier layer.

Abstract: A data management method for a solid state storage device is provided. The solid state storage device can selectively perform a TACW operation. While the TACW operation is performed, the controlling circuit determines a specified time interval corresponding to the largest amount of write data. Moreover, a portion of the write data stored in the specific time interval will be moved to another location of the non-volatile memory. When the solid state storage device performs the data remediation process according to the data retention time, the time period of performing the data remediation process is largely shortened. Consequently, the performance of the solid state storage device can be enhanced.

Abstract: In some examples, a computer-readable medium storing executable code which, when executed by a processor of an electronic device, causes the processor to store a relationship between a user eye gaze pattern and first conditions of the electronic device, identify second conditions of the electronic device, determine whether the second conditions match the first conditions, and responsive to the second conditions matching the first conditions, selectively operate a display panel of the electronic device with differing display characteristics based on the user eye gaze pattern.

Abstract: An electronic device includes a memory usage identification circuit and a system-level cache (SLC). The memory usage identification circuit obtains a memory usage indicator that depends on memory usage of a storage space allocated in a system memory at which memory access is requested by a physical address. The SLC includes a cache memory and a cache controller. The cache controller performs cache management upon the cache memory according to the physical address and the memory usage indicator.