Abstract: A thermally enhanced electronic package comprises a driver chip, an insulator, a flexible carrier, and carbon nanocapsules. The flexible carrier includes a flexible substrate, a wiring layer formed on the substrate, and a resistant overlaying the wiring layer. The driver chip is connected to the wiring layer. The insulator is filled in the gap between the driver chip and the flexible carrier. The carbon nanocapsules are disposed on the driver chip, on the resistant, on the flexible carrier, or in the insulator to enhance heat dissipation of electronic packages.

Abstract: A thermally enhanced electronic package comprises a driver chip, an insulator, a flexible carrier, and carbon nanocapsules. The flexible carrier includes a flexible substrate, a wiring layer formed on the substrate, and a resistant overlaying the wiring layer. The driver chip is connected to the wiring layer. The insulator is filled in the gap between the driver chip and the flexible carrier. The carbon nanocapsules are disposed on the driver chip, on the resistant, on the flexible carrier, or in the insulator to enhance heat dissipation of electronic packages.

Abstract: A thermally enhanced electronic package comprises a driver chip, an insulator, a flexible carrier, and carbon nanocapsules. The flexible carrier includes a flexible substrate, a wiring layer formed on the substrate, and a resistant overlaying the wiring layer. The driver chip is connected to the wiring layer. The insulator is filled in the gap between the driver chip and the flexible carrier. The carbon nanocapsules are disposed on the driver chip, on the resistant, on the flexible carrier, or in the insulator to enhance heat dissipation of electronic packages.

Abstract: A flip-chip package structure comprising a substrate, a chip, a bump structure and a solder resist is provided. The substrate has a circuit layer disposed on the surface thereof. The chip comprises a central region and two edge regions disposed on the two sides of the central region. The bump structure is disposed on the central region of the chip and faces the substrate. The solder resist is disposed on the substrate to partially cover the circuit layer. The chip is electrically connected to the substrate by the bump structure, and the solder resist is adapted to come into contact with the two edge regions of the chip to support the chip with the bump structure when the chip is disposed on the substrate.

Abstract: A thermally enhanced electronic package comprises a driver chip, an insulator, a flexible carrier, and carbon nanocapsules. The flexible carrier includes a flexible substrate, a wiring layer formed on the substrate, and a resistant overlaying the wiring layer. The driver chip is connected to the wiring layer. The insulator is filled in the gap between the driver chip and the flexible carrier. The carbon nanocapsules are disposed on the driver chip, on the resistant, on the flexible carrier, or in the insulator to enhance heat dissipation of electronic packages.

Abstract: A method for use in manufacturing a microelectromechanical system, such as a reflective stealth mirror includes the steps of: forming an I-shape mirror structure; forming a spacer layer over the I-shape mirror structure; and patterning the spacer layer to form at least one spacer along a side of the I-shape mirror structure.

Abstract: An in-situ performed method utilizing a pure H2O plasma to remove a layer of resist from a substrate or wafer without substantially accumulating charges thereon. Also, in-situ performed methods utilizing a pure H2O plasma or a pure H2O vapor to release or remove charges from a surface or surfaces of a substrate or wafer that have accumulated during one or more IC fabrication processes.

Abstract: The invention provides a flexible substrate for package of a semiconductor die. The flexible substrate includes a flexible insulating film, a plurality of first leads substantially formed on the flexible insulating film, and at least one loop-shaped second lead substantially formed on the flexible insulating film. The at least one second lead is partially disposed at a corner of a device hole of the flexible film, and is designed as being capable of preventing from fracture induced during the package of the semiconductor die. Preferably, the portion of each of the at least one second lead, to be overlapped over the semiconductor die, exhibits an L-shape, a U-shape or a Y-shape.

Abstract: The invention provides a tape for a tape carrier package. The tape includes a flexible insulating film. The flexible insulating film is divided into a plurality of units arranged successively, and each of the units has a device hole and a plurality of leads. The plurality of leads are formed on the flexible insulating film and protrude to the device hole. The device hole has a plurality of corners formed in a form of a notch for preventing the stress from concentrating on and breaking the leads.

Abstract: The process of the present invention comprises reactive ion etching of AlxFyOz oxide deposits on aluminum-containing bond pads using feed gases, such as, SF6/CF4/Ar or Cl2/BCL3/Ar. whose active plasma etches the AlxFyOz oxide deposits by physical etching and chemical etching for more complete removal of the AlxFyOz oxide deposits.

Abstract: A method for use in manufacturing a microelectromechanical system, such as a reflective stealth mirror includes the steps of: forming an I-shape mirror structure; forming a spacer layer over the I-shape mirror structure; and patterning the spacer layer to form at least one spacer along a side of the I-shape mirror structure.

Abstract: The process of the present invention comprises reactive ion etching of AlxFyOz oxide deposits on aluminum-containing bond pads using feed gases, such as, SF6/CF4/Ar or Cl2/BCL3/Ar. whose active plasma etches the AlxFyOz oxide deposits by physical etching and chemical etching for more complete removal of the AlxFyOz oxide deposits.

Abstract: A method of forming very small silicon nitride spacers in split-gate flash EPROMs is disclosed which prevent the occurrence of “write disturb”, unwanted reverse tunneling, or erasing. This is accomplished by forming spacers with well-controlled dimensions and well-defined shapes through a judicious use of a fully wet etch technique, including main-etch and over-etch. The use of a phosphoric acid solution in combination with sulfuric acid+hydrogen peroxide widens the process window from a few seconds to several minutes so that the small-dimensioned silicon nitride spacers can be better controlled than it has been possible in the past. In the first embodiment phosphoric solution is used both for main-etch and for over-etch. In the second embodiment, phosphoric solution is used for main-etch only, while the sulfuric+hydrogen peroxide solution is used as an over-etch in forming the tiny silicon nitride spacers of the invention.

Abstract: A method for a metal etchback process to form a metal filled semiconductor feature having improved planarity and electrical resistance including a semiconductor wafer having an etched opening lined with a refractory metal containing layer and a blanket deposited metal layer filling the etched opening; spin coating a spin on layer selected from the group consisting of an organic resinous layer and a spin-on glass layer over the metal layer; dry etching in a first etchback process to remove a first portion of the SOL layer to reveal a portion of the metal layer leaving a second portion of the SOL layer overlying the etched opening; dry etching in a second etchback process to remove the metal layer to reveal a portion of the refractory metal containing layer; and, removing the second portion of the SOL layer to form a substantially planar metal filled etched opening.

Abstract: A method of forming very small silicon nitride spacers in split-gate flash EPROMs is disclosed which prevent the occurrence of “write disturb”, unwanted reverse tunneling, or erasing. This is accomplished by forming spacers with well-controlled dimensions and well-defined shapes through a judicious use of a fully wet etch technique, including main-etch and over-etch. The use of a phosphoric acid solution in combination with sulfuric acid+hydrogen peroxide widens the process window from a few seconds to several minutes so that the small-dimensioned silicon nitride spacers can be better controlled than it has been possible in the past. In the first embodiment phosphoric solution is used both for main-etch and for over-etch. In the second embodiment, phosphoric solution is used for main-etch only, while the sulfuric+hydrogen peroxide solution is used as an over-etch in forming the tiny silicon nitride spacers of the invention.

Abstract: A method for a metal etchback process to form a metal filled semiconductor feature having improved planarity and electrical resistance including a semiconductor wafer having an etched opening lined with a refractory metal containing layer and a blanket deposited metal layer filling the etched opening; spin coating a spin on layer selected from the group consisting of an organic resinous layer and a spin-on glass layer over the metal layer; dry etching in a first etchback process to remove a first portion of the SOL layer to reveal a portion of the metal layer leaving a second portion of the SOL layer overlying the etched opening; dry etching in a second etchback process to remove the metal layer to reveal a portion of the refractory metal containing layer; and, removing the second portion of the SOL layer to form a substantially planar metal filled etched opening.

Abstract: A method of forming very small silicon nitride spacers in split-gate flash EPROMs is disclosed which prevent the occurrence of “write disturb”, unwanted reverse tunneling, or erasing. This is accomplished by forming spacers with well controlled dimensions and well defined shapes through a judicious combination of dry etch with wet over-etch technique. The wet etch along with the dry etch widens the process window from a few seconds to several minutes so that the small dimensioned silicon nitride spacers can be better controlled than it has been possible in the past. In a second embodiment, the step of over-etching of the spacers is combined with the step of stripping off of an implant photomask, thus, shortening the manufacturing product cycle.