Patents by Inventor Hung-Hsu Feng

Hung-Hsu Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Connectivity-aware layout data reduction for design verification
    Patent number: 9785736
    Abstract: Aspects of the disclosed technology relate to techniques of connectivity-aware reduction of layout data. With various implementations of the disclosed technology, circuit elements of interest are selected in a circuit design which includes netlist information and layout data. Based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, nets of interest are determined. Cells of interest, comprising cells that are identified based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, are then determined. Based on the nets of interest and the cells of interest, layout geometric elements are selected and may be analyzed for design verification. For electrostatic discharge (ESD) protection verification, the cells of interest may further comprise cells that include portions of power supply grids on top metal layers.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: October 10, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Yi-Ting Lee, Sridhar Srinivasan, Hung-Hsu Feng
  • Connectivity-Aware Layout Data Reduction For Design Verification
    Publication number: 20160063172
    Abstract: Aspects of the disclosed technology relate to techniques of connectivity-aware reduction of layout data. With various implementations of the disclosed technology, circuit elements of interest are selected in a circuit design which includes netlist information and layout data. Based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, nets of interest are determined. Cells of interest, comprising cells that are identified based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, are then determined. Based on the nets of interest and the cells of interest, layout geometric elements are selected and may be analyzed for design verification. For electrostatic discharge (ESD) protection verification, the cells of interest may further comprise cells that include portions of power supply grids on top metal layers.
    Type: Application
    Filed: March 19, 2015
    Publication date: March 3, 2016
    Inventors: Yi-Ting Lee, Sridhar Srinivasan, Hung-Hsu Feng