Patents by Inventor Hung-Hsun CHEN

Hung-Hsun CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210125885
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 29, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao
  • Publication number: 20210013234
    Abstract: An electronic device is provided. The electronic device includes a substrate, a first gate circuit, a second gate circuit, a signal line, and a shielding layer. The substrate includes a display area and a peripheral area. The first gate circuit is disposed in the peripheral area. The second gate circuit is disposed in the peripheral area. The signal line is coupled between the first gate circuit and the second gate circuit. The signal line includes a specific line segment, and the specific line segment overlaps the display area. The shielding layer is disposed in the display area. The shielding layer overlaps the specific line segment.
    Type: Application
    Filed: June 22, 2020
    Publication date: January 14, 2021
    Inventors: Yu-Che CHANG, Li-Wei SUNG, Cheng-Tso CHEN, Hui-Min HUANG, Chia-Min YEH, Hung-Hsun CHEN
  • Patent number: 10770014
    Abstract: A display device includes a display panel having a display region and a peripheral region. The display panel includes a substrate and a scan driving circuit. The scan driving circuit disposed on the substrate includes a plurality of scan driving blocks and a plurality of first conductive lines. The first conductive lines are respectively coupled to and disposed between adjacent scan driving blocks. The scan driving blocks are disposed corresponding to the peripheral region, and the first conductive lines are disposed corresponding to the display region and the peripheral region.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: September 8, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Min Yeh, Hung-Hsun Chen, Hui-Min Huang, Cheng-Tso Chen, Li-Wei Sung
  • Publication number: 20190304392
    Abstract: A display device includes a display panel having a display region and a peripheral region. The display panel includes a substrate and a scan driving circuit. The scan driving circuit disposed on the substrate includes a plurality of scan driving blocks and a plurality of first conductive lines. The first conductive lines are respectively coupled to and disposed between adjacent scan driving blocks. The scan driving blocks are disposed corresponding to the peripheral region, and the first conductive lines are disposed corresponding to the display region and the peripheral region.
    Type: Application
    Filed: March 12, 2019
    Publication date: October 3, 2019
    Inventors: Chia-Min YEH, Hung-Hsun CHEN, Hui-Min HUANG, Cheng-Tso CHEN, Li-Wei SUNG
  • Patent number: 10146346
    Abstract: A touch display device including a touch display panel and a data line driving circuit is provided. The touch display panel includes a plurality of pixels and a first shift register unit. The first shift register unit provides a first shifted signal to a first portion of the pixels. A first transistor receives a clock signal, is coupled to an output node, and outputs the first shifted signal. A second transistor receives a first trigger signal, is coupled to the first transistor. A third transistor is coupled to the second transistor, receives a first operation voltage and a second trigger signal. A fourth transistor is coupled to the first source, receives a second operation voltage and the second trigger signal. A capacitor is coupled between the first transistor and stacked by a first metal layer, a second metal layer, and a third metal layer.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: December 4, 2018
    Assignee: INNOLUX CORPORATION
    Inventors: Li-Wei Sung, Yu-Chien Kao, Hsieh-Li Chou, Yu-Ti Huang, Yu-Che Chang, Chung-Le Chen, Hung-Hsun Chen
  • Patent number: 10031614
    Abstract: A touch display panel driven in a display period and a touch period alternately is provided, and includes a plurality of gate lines, each driven by a clock signal to output a scan signal during the display period and stop the scan signal during the touch period; and N dummy gate lines, each driven by a dummy clock signal to output a dummy scan signal before the display period is switched to the touch period, wherein at least one of rising edges of N dummy clock signals is synchronized with at least one of falling edges of the clock signals.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: July 24, 2018
    Assignee: INNOLUX CORPORATION
    Inventors: Li-Wei Sung, Chung-Le Chen, Hung-Hsun Chen, Yang-Chen Chen, Chia-Hsiung Chang
  • Publication number: 20180053791
    Abstract: An array substrate includes a substrate, a first transistor and an optical modulating layer. The first transistor is disposed on the substrate and includes a first semiconductor layer having a first channel region. A first gate is disposed on the first semiconductor layer. First source and first drain are electrically connected to the first semiconductor layer respectively. A first interval is located between the first source and the first drain and the first channel region corresponds to the first interval. A first insulating layer is disposed between the first semiconductor layer and the first gate. A second insulating layer covers the first source, the first drain and the first channel region. The optical modulating layer is disposed on the second insulating layer and has an optical density (OD) in greater than or equal to 0.1 and less than or equal to 6.
    Type: Application
    Filed: July 5, 2017
    Publication date: February 22, 2018
    Inventors: Li-Wei SUNG, Fu-Yuan HSIAO, Chung-Le CHEN, Hung-Hsun CHEN
  • Publication number: 20170003804
    Abstract: A touch display panel driven in a display period and a touch period alternately is provided, and includes a plurality of gate lines, each driven by a clock signal to output a scan signal during the display period and stop the scan signal during the touch period; and N dummy gate lines, each driven by a dummy clock signal to output a dummy scan signal before the display period is switched to the touch period, wherein at least one of rising edges of N dummy clock signals is synchronized with at least one of falling edges of the clock signals.
    Type: Application
    Filed: June 23, 2016
    Publication date: January 5, 2017
    Inventors: Li-Wei SUNG, Chung-Le CHEN, Hung-Hsun CHEN, Yang-Chen CHEN, Chia-Hsiung CHANG
  • Publication number: 20160216820
    Abstract: A touch display device including a touch display panel and a data line driving circuit is provided. The touch display panel includes a plurality of pixels and a first shift register unit. The first shift register unit provides a first shifted signal to a first portion of the pixels. A first transistor receives a clock signal, is coupled to an output node, and outputs the first shifted signal. A second transistor receives a first trigger signal, is coupled to the first transistor. A third transistor is coupled to the second transistor, receives a first operation voltage and a second trigger signal. A fourth transistor is coupled to the first source, receives a second operation voltage and the second trigger signal. A capacitor is coupled between the first transistor and stacked by a first metal layer, a second metal layer, and a third metal layer.
    Type: Application
    Filed: January 7, 2016
    Publication date: July 28, 2016
    Inventors: Li-Wei SUNG, Yu-Chien KAO, Hsieh-Li CHOU, Yu-Ti HUANG, Yu-Che CHANG, Chung-Le CHEN, Hung-Hsun CHEN