Patents by Inventor Hung-Hsun Lin

Hung-Hsun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12199033
    Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: January 14, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung Hsun Lin, Wei-Chun Hua, Wen-Chu Huang, Yen-Yu Chen, Che-Chih Hsu, Chinyu Su, Wen Han Hung
  • Patent number: 12087627
    Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung Hsun Lin, Che-Chih Hsu, Wen-Chu Huang, Chinyu Su, Yen-Yu Chen, Wei-Chun Hua, Wen Han Hung
  • Publication number: 20230223335
    Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
    Type: Application
    Filed: March 7, 2023
    Publication date: July 13, 2023
    Inventors: Hung Hsun LIN, Wei-Chun HUA, Wen-Chu HUANG, Yen-Yu CHEN, Che-Chih HSU, Chinyu SU, Wen Han HUNG
  • Patent number: 11616013
    Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: March 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung Hsun Lin, Che-Chih Hsu, Wen-Chu Huang, Chinyu Su, Yen-Yu Chen, Wei-Chun Hua, Wen Han Hung
  • Publication number: 20220367343
    Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 17, 2022
    Inventors: Hung Hsun Lin, Che-Chih Hsu, Wen-Chu Huang, Chinyu Su, Yen-Yu Chen, Wei-Chun Hua, Wen Han Hung
  • Publication number: 20210391251
    Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Inventors: Hung Hsun Lin, Che-Chih Hsu, Wen-Chu Huang, Chinyu Su, Yen-Yu Chen, Wei-Chun Hua, Wen Han Hung
  • Patent number: 10825508
    Abstract: A bit line structure for two-transistor static random access memory (2T SRAM), including multiple bit lines extending over multiple 2T SRAMs in a first direction, wherein each bit line consists of multiple first portions and second portions extending in the first direction and electrically connecting with each other in an alternating manner, and the first portions and the second portions are in a first dielectric layer and a second dielectric layer respectively, and the first portions of each bit line correspond to the second portions of adjacent bit lines.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: November 3, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Pei-Hsiu Tseng, I-Shuan Wei, Jia-You Lin, Shou-Zen Chang, Chi-Wei Lin, Hung-Hsun Lin