Abstract: An image sensor is provided. The image sensor includes a substrate, an isolation structure on the substrate, a photoelectric conversion layer, a transparent electrode layer, an encapsulation layer, a color filter layer, and a micro-lens. The isolation structure is electrically non-conductive and defines a plurality of pixel regions on the substrate. The isolation structure prevents cross-talk of electrical signals among pixels. The photoelectric conversion layer is disposed on the pixel regions defined by the isolation structure. The transparent electrode layer is disposed over the isolation structure and the photoelectric conversion layer. The encapsulation layer is disposed over the transparent electrode layer. The micro-lens is disposed on the color filter layer.

Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.

Abstract: A solid-state image sensor having a first region and a second region adjacent to the first region along a first direction is provided. The solid-state image sensor includes a first unit pattern disposed in the first region. The solid-state image sensor also includes a second unit pattern disposed in the second region and corresponding to the first unit pattern. The first unit pattern and the second unit pattern each includes normal pixels and an auto-focus pixel array. The normal pixels and the auto-focus pixel array in the first unit pattern form a first arrangement, the normal pixels and the auto-focus pixel array in the second unit pattern form a second arrangement, and the first arrangement and the second arrangement are symmetric with respect to the first axis of symmetry.

Abstract: A solid-state image sensor having a first region and a second region adjacent to the first region along a first direction is provided. The solid-state image sensor includes a first unit pattern disposed in the first region. The solid-state image sensor also includes a second unit pattern disposed in the second region and corresponding to the first unit pattern. The first unit pattern and the second unit pattern each includes normal pixels and an auto-focus pixel array. The normal pixels and the auto-focus pixel array in the first unit pattern form a first arrangement, the normal pixels and the auto-focus pixel array in the second unit pattern form a second arrangement, and the first arrangement and the second arrangement are symmetric with respect to the first axis of symmetry.

Abstract: An optical device is provided. The optical device includes a substrate and a plurality of optical structures. The substrate includes a plurality of photoelectric conversion elements. The optical structures are disposed above the substrate. Each optical structure corresponds to one photoelectric conversion element. Each optical structure includes a first portion and a second portion. The first portion has a first glass transition temperature. The second portion has a second glass transition temperature. The second portion guides the incident light into the photoelectric conversion element. The first glass transition temperature is higher than the second glass transition temperature.

Abstract: A circuit for detecting a clock has a plurality of first transmission elements, a plurality of first exclusive OR gates and a first AND gate. Each first transmission element is coupled to a last first transmission element for receiving output data, and the data received by each first transmission element is transmitted to an input terminal of a next first transmission element. In addition, the input of a first transmission element is coupled to a clock source for receiving a predetermined clock signal of which a frequency is less than a frequency of a local clock signal. Furthermore, the first and second input terminals of a kth exclusive OR gate are coupled to output terminals of a kth and a (k+1)th first transmission elements, wherein k is an integer greater than 0 smaller than a total number of the first transmission elements.

Abstract: A circuit for detecting a clock has a plurality of first transmission elements, a plurality of first exclusive OR gates and a first AND gate. Each first transmission element is coupled to a last first transmission element for receiving output data, and the data received by each first transmission element is transmitted to an input terminal of a next first transmission element. In addition, the input of a first transmission element is coupled to a clock source for receiving a predetermined clock signal of which a frequency is less than a frequency of a local clock signal. Furthermore, the first and second input terminals of a kth exclusive OR gate are coupled to output terminals of a kth and a (k+1)th first transmission elements, wherein k is an integer greater than 0 smaller than a total number of the first transmission elements.

Abstract: A method and system for preventing white pixel difficulties resulting from undesired current induced in an image sensor having a photodiode and a depletion region therein. The photodiode is isolated in a pixel layout for an image sensor. A depletion region is configured, such that the depletion region is maintained in a defect-free region associated with the pixel layout for the image sensor, thereby reducing white pixel difficulties caused by induced and undesired current. The image sensor is preferably a CMOS image sensor. A depletion region of the photodiode is constantly maintained in a defect-free region during operation of the CMOS image sensor.

Abstract: An arithmetic unit which performs all basic arithmetic operations in a finite field GF(2m) and includes an arithmetic processor, an arithmetic logic unit and a control unit is disclosed. The arithmetic unit of the present invention is structured with a low circuit complexity, so that an error-correcting decoder applying this calculating processor can be greatly simplified.

Abstract: A method and system for preventing white pixel difficulties resulting from undesired current induced in an image sensor having a photodiode and a depletion region therein. The photodiode is isolated in a pixel layout for an image sensor. A depletion region is configured, such that the depletion region is maintained in a defect-free region associated with the pixel layout for the image sensor, thereby reducing white pixel difficulties caused by induced and undesired current. The image sensor is preferably a CMOS image sensor. A depletion region of the photodiode is constantly maintained in a defect-free region during operation of the CMOS image sensor.

Abstract: A method and an apparatus for preparing a backside-ground wafer for testing are described. The method includes the steps of first providing a calibration wafer that has a pattern formed on a top surface of an insulating material such as oxide or nitride. Three droplets of water are applied with each droplet sufficiently apart from the other droplets on the top surface of the calibration wafer. A backside-ground wafer that has a ground backside and a front side to be tested is then mated to the calibration wafer by mating the ground backside to the top surface of the calibration wafer with water droplets therein-between forming a bond by capillary reaction in-between the oxide pattern on the calibration wafer. The apparatus for mounting a backside-ground wafer to a calibration wafer consists of a slanted block having a top surface with a slant angle between about 10° and about 30°.

Abstract: The invention provides a method of fabricating corrosion free metal lines. The method involves forming a thin polymeric passivation layer 30 over the metal layer 20 immediately after the metal deposition and before any photolithographic or etching processes. The polymeric passivation layer 30 is formed using a F-containing gas plasma treatment. The passivation layer prevents corrosion of the metal layer before a metal etch. The passivation layer is preferably composed of a polymeric of C, O, and F and has a thickness in a range of between about 40 and 80 .ANG.. The passivation layer is formed using a F-containing plasma treatment at a power of between 225 and 275 W, a pressure between about 80 and 120 mtorr, a CHF.sub.3 flow between about 40 and 60 sccm and for a duration between about 10 to 30 seconds. Following this, the metal layer is patterned using photo and etch steps.