Abstract: Devices and method for forming a switch including a heater layer including a first heater pad, a second heater pad, and a heater line connecting the first heater pad and the second heater pad, a phase change material (PCM) layer positioned in a same vertical plane as the heater line, and a floating spreader layer including a first portion positioned in the same vertical plane as the heater line and the PCM layer, in which the first portion has a first width that is less than or equal to a distance between proximate sidewalls of the first heater pad and the second heater pad.

Abstract: The disclosure provides an integrated circuit and an operation method and an inspection method thereof. The integrated circuit includes a one-time programmable (OTP) memory, an identifier generation circuit, and a memory controller. The identifier generation circuit generates a random number, and performs an error-detection-code encoding operation on the random number to generate an identifier with an error-detection code. The memory controller writes the identifier generated by the identifier generation circuit into the OTP memory. The identifier generation circuit reads the identifier from the OTP memory through the memory controller, and performs an error-detection-code decoding operation on the identifier provided by the memory controller to determine whether an error of the identifier from the OTP memory is correctable. When it is determined that the error of the identifier from the OTP memory is not correctable, the writing of the identifier is deemed failed.

Abstract: An image processing apparatus is disclosed, which comprises a rasterization engine, a texture mapping module and a destination buffer. The rasterization engine receives a group of vertices from a vertex list and performs polygon rasterization operations for a point within the group of vertices forming a polygon to generate texture coordinates for each camera image. The vertex list comprises a plurality of vertices with their data structures. The texture mapping module texture maps texture data from each camera image according to its texture coordinates to generate a sample value for each camera image. The destination buffer is coupled to the texture mapping module and stores the panoramic image. Here, the data structures define a mapping between the panoramic image and the camera images.

Abstract: A System on Chip (SOC) is disclosed. The SOC comprises a first UART controller, a second UART controller, a debug controller, a processor, a UART port, a first multiplexer and a second multiplexer. The first UART controller and the second UART controller have different baud rates. The UART port has a R×D pin coupled to a R×D pin of the second UART controller. The debug controller generates a control signal with a first state and checks whether a received data from the UART controller is equal to a keyword after power-up or a hardware reset. When the received data from the second UART controller is equal to the keyword, the debug controller generates the control signal with the second state, and starts parsing and executing at least one debug command from the second UART controller.

Abstract: A System on Chip (SOC) is disclosed. The SOC comprises a first UART controller, a second UART controller, a debug controller, a processor, a UART port, a first multiplexer and a second multiplexer. The first UART controller and the second UART controller have different baud rates. The UART port has a R×D pin coupled to a R×D pin of the second UART controller. The debug controller generates a control signal with a first state and checks whether a received data from the UART controller is equal to a keyword after power-up or a hardware reset. When the received data from the second UART controller is equal to the keyword, the debug controller generates the control signal with the second state, and starts parsing and executing at least one debug command from the second UART controller.

Abstract: A method of accessing a desired memory location applied in a cipher processing apparatus is disclosed. The cipher processing apparatus comprises a plurality of registers and a register storage. The method comprises the steps of: reading a cipher instruction comprising an opcode field and an operand specifier field; reading a base address from one of the plurality of registers according to a register-id sub-field; respectively reading a bit length and an index value from the register storage and an index sub-field; determining the desired memory location according to the base address, the bit length and the index value; and, accessing the desired memory location to obtain a desired field variable. Here, the operand specifier field comprises the register-id sub-field and the index sub-field.

Abstract: A baseboard management system suitable for use in a high density server system is provided. The baseboard management system comprises: a plurality of baseboard management controller (BMC) node respectively located on the servers; and, a main BMC coupled to a network and to the BMC nodes through a communication link for executing a management software; wherein each BMC node is connected with a corresponding host processor and with server board peripherals individually on a corresponding server; and wherein the main BMC in cooperation with the BMC nodes is used to manage the servers remotely.

Abstract: An auto firmware update device and method for fault-tolerance is provided. According to an embodiment of the invention, the auto firmware update device includes a serial port, a processor, a timer, a memory and a control unit. The serial port is used for coupling to an external device and updating firmware. The processor fetches instructions to boot. The timer is configured to start counting when the processor boots or restart each time, wherein the timer generates an alarm signal if the timer expires before the processor successfully boots. The memory stores a copy of firmware for booting. The control unit receives the alarm signal to stop the processor, downloads another copy of firmware for booting through the serial port to write to the memory, and restarts the processor.

Abstract: An integrated circuit with automatic configuration is disclosed. The integrated circuit comprises a plurality of controllers and a clock detection device. The controllers share a plurality of common pins. The clock detection device coupled to a specified common pin for performing clock detection operations on an external clock signal through the specified common pin according to a plurality of predetermined thresholds and generating a plurality of control signals to the controllers so that only one controller is enabled and performs signal transmission through the common pins.

Abstract: A baseboard management controller is disclosed. The baseboard management controller adapted to monitor a host comprises a baseboard management control module, a memory controller and a video graphic array (VGA) module. The VGA module comprises a video controller, a decoder, a select circuit and a mapping circuit. The decoder receives a transaction signal from a first local bus and decodes a first address signal contained in the transaction signal. The select circuit selectively transfers data from one of the microprocessor bus, the video controller and the memory controller back to the first local bus according to a control signal. The mapping circuit being connected with the decoder maps the first address signal and a second address signal to a third address signal, updates the first address signal and transfers an updated transaction signal.

Abstract: The invention discloses a transmitting apparatus. The transmitting apparatus uses the same transmission medium to transmit two signals that are within different frequency ranges at the same time. The transmitting apparatus increases the transmitting paths of the transmission medium so as to enhance the use of the transmission medium and save the production costs.

Abstract: A baseboard management controller is disclosed. The baseboard management controller adapted to monitor a host comprises a baseboard management control module, a memory controller and a video graphic array (VGA) module. The VGA module comprises a video controller, a decoder, a select circuit and a mapping circuit. The decoder receives a transaction signal from a first local bus and decodes a first address signal contained in the transaction signal. The select circuit selectively transfers data from one of the microprocessor bus, the video controller and the memory controller back to the first local bus according to a control signal. The mapping circuit being connected with the decoder maps the first address signal and a second address signal to a third address signal, updates the first address signal and transfers an updated transaction signal.

Abstract: The present invention provides a remote control system for a power supply, comprising: a display data channel (DDC); a first control circuit electrically connected to said DDC, coding and sending a control signal through said DDC to control said power supply; a second control circuit electrically connected to said DDC, receiving and decoding said control signal through said DDC to control said power supply.

Abstract: The invention discloses a distant PCIe extended system. The distant PCIe extended system includes a local PCIe virtualization device (PVD), at least a transmission medium and at least a remote PVD. The PVD includes a PCIe PHY layer, a signal converting circuit, at least a PVD PHY layer and a transmission medium. The PCIe PHY layer is used to receive a PCIe physical signal. The signal converting circuit is coupled to the PCIe PHY layer and used to convert the PCIe data link layer packet into at least a PVD MAC packet. The PVD PHY layer is coupled to the signal converting circuit and used to process and transfer the PVD MAC packet. The transmission medium receives and transfers the PVD physical signal.

Abstract: The invention discloses a transmitting apparatus. The transmitting apparatus uses the same transmission medium to transmit two signals that are within different frequency ranges at the same time. The transmitting apparatus increases the transmitting paths of the transmission medium so as to enhance the use of the transmission medium and save the production costs.

Abstract: A remote multiple image processing apparatus comprises a graphic processing unit, a memory unit, an image compression unit, a transmission unit and a transmission medium. The graphic processing unit receives at least an image frame including a plurality of image blocks, and determines the degree of the difference between the current input image block and the previous input image block. The memory unit, coupling to the graphic processing unit, stores the image blocks. The image compression unit, coupling to the memory unit, compresses the image blocks and generates at least a compressed datum. The transmission unit, coupling to the image compression unit, transforms the compressed datum into at least a data packet. The transmission medium outputs the data packet. The remote multiple image processing apparatus uses the compression technique to allow a client sharing the resources of graphic processing unit so as to get multiple use benefits.

Abstract: A progressive differential motion JPEG codec is disclosed. The compression encoder of the progressive differential motion JPEG codec comprises a video capture unit, a video capture buffer, a detection unit, a compression unit, and a quality level buffer. The video capture unit is used for receiving an image data and dividing a component of the image data into a plurality of image data blocks. The video capture buffer stores the image data block. The detection unit is electrically coupled to the video capture unit and the video capture buffer for detecting whether a content of the image data block input from the video capture unit is different from a content of the image data block retrieved from the video capture buffer.

Abstract: The invention discloses a transmission device. The transmission device includes an interface circuit, a data converting circuit, at least a physical layer and a transmission medium. The interface circuit is used to receive a PCIe signal or a PCI signal. The data converting circuit is coupled to the interface circuit and used to convert the PCIe signal or the PCI signal into at least a data packet. The physical layer is coupled to the data converting circuit and used to process and transfer the data packet. The transmission medium receives and transfers the data packet.

Abstract: The present invention provides a remote control system for a power supply, comprising a display data channel (DDC); a first control circuit electrically connected to said DDC, coding and sending a control signal through said DDC to control said power supply; a second control circuit electrically connected to said DDC, receiving and decoding said control signal through said DDC to control said power supply.

Abstract: An apparatus and method for data capture with multi-threshold decision technique is disclosed. An apparatus for data capture with multi-threshold decision technique comprises a capture engine unit being operative to captures data from a video source, a buffer unit being operative to store the captured data by the capture engine unit, and a comparison unit being operative to compare the captured data stored in the buffer unit with a newly captured data outputted from the capture engine unit, wherein the comparison unit utilizes different thresholds to distinguish the difference degree between the captured data stored in the buffer unit and a newly captured data outputted from the capture engine unit so as to determine whether performing data update or not.