Patents by Inventor Hung-Jui Kou

Hung-Jui Kou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10586724
    Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: March 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Chung-Shi Liu, Hung-Jui Kou, Ming-Da Cheng
  • Patent number: 10297494
    Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Jing-Cheng Lin, Hung-Jui Kou
  • Patent number: 10186462
    Abstract: A semiconductor device and method includes forming a conductive post on a die; coupling a test probe to the conductive post with solder; and etching the solder and the conductive post with a plurality of etching processes, the plurality of etching processes including a first etching process, the first etching process comprising etching the conductive post with a nitric-based etchant.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: January 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hui-Jung Tsai, Yun Chen Hsieh, Hung-Jui Kou
  • Patent number: 10049889
    Abstract: Some embodiments contemplate methods for forming a package structure and a package structure formed thereby. An embodiment method includes depositing a photosensitive dielectric layer on a support structure; forming a first layer on a surface of the photosensitive dielectric layer; exposing the photosensitive dielectric layer to radiation; and after the forming the first layer and the exposing to radiation, developing the photosensitive dielectric layer. The support structure includes an integrated circuit die. The layer has a different removal selectivity than the photosensitive dielectric layer during the developing. According to some embodiments, a thickness uniformity of the photosensitive dielectric layer after developing may be increased, and thickness loss from developing the photosensitive dielectric layer can be reduced.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Chung-Shi Liu, Hung-Jui Kou, Sih-Hao Liao
  • Publication number: 20180211912
    Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.
    Type: Application
    Filed: July 3, 2017
    Publication date: July 26, 2018
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Jing-Cheng Lin, Hung-Jui Kou
  • Publication number: 20180151453
    Abstract: A semiconductor device and method includes forming a conductive post on a die; coupling a test probe to the conductive post with solder; and etching the solder and the conductive post with a plurality of etching processes, the plurality of etching processes including a first etching process, the first etching process comprising etching the conductive post with a nitric-based etchant.
    Type: Application
    Filed: July 3, 2017
    Publication date: May 31, 2018
    Inventors: Chen-Hua Yu, Hui-Jung Tsai, Yun Chen Hsieh, Hung-Jui Kou
  • Patent number: 9941140
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads may be arranged in a ball grid array (BGA), and the may include a plurality of corners. A metal dam is disposed around each of the plurality of corners, such as corners of the BGA.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Feng Chen, Kai-Chiang Wu, Chun-Lin Lu, Hung-Jui Kou
  • Publication number: 20170345675
    Abstract: Some embodiments contemplate methods for forming a package structure and a package structure formed thereby. An embodiment method includes depositing a photosensitive dielectric layer on a support structure; forming a first layer on a surface of the photosensitive dielectric layer; exposing the photosensitive dielectric layer to radiation; and after the forming the first layer and the exposing to radiation, developing the photosensitive dielectric layer. The support structure includes an integrated circuit die. The layer has a different removal selectivity than the photosensitive dielectric layer during the developing. According to some embodiments, a thickness uniformity of the photosensitive dielectric layer after developing may be increased, and thickness loss from developing the photosensitive dielectric layer can be reduced.
    Type: Application
    Filed: August 18, 2017
    Publication date: November 30, 2017
    Inventors: Yu-Hsiang Hu, Chung-Shi Liu, Hung-Jui Kou, Sih-Hao Liao
  • Publication number: 20170263489
    Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 14, 2017
    Inventors: Yu-Hsiang Hu, Chung-Shi Liu, Hung-Jui Kou, Ming-Da Cheng