Patents by Inventor Hung Jui Kuo

Hung Jui Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED FAN-OUT (INFO) PACKAGE STRUCTURE
    Publication number: 20220310519
    Abstract: Provided is an integrated fan-out (InFO) package structure including a first die, a second die, a third die, a protective layer, and an interconnect structure. The first die has a first surface and a second surface opposite to each other. The first die has a plurality of through substrate vias (TSVs) protruding from the second surface. The second die and the third die are bonded on the first surface of the first die. The protective layer laterally surrounds protrusions of the plurality of TSVs that protrude from the second surface. The interconnect structure are disposed on the protective layer and electrically connected to the plurality of TSVs. The interconnect structure includes a polymer layer covering the protective layer.
    Type: Application
    Filed: June 15, 2022
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Ho, Hung-Jui Kuo, Tzung-Hui Lee
  • Semiconductor device and method of manufacture
    Patent number: 11454888
    Abstract: A method of manufacturing a semiconductor device includes forming a polymer mixture over a substrate, curing the polymer mixture to form a polymer material, and patterning the polymer material. The polymer mixture includes a polymer precursor, a photosensitizer, a cross-linker, and a solvent. The polymer precursor may be a polyamic acid ester. The cross-linker may be tetraethylene glycol dimethacrylate. The photosensitizer includes 4-phenyl-2-(piperazin-1-yl)thiazole. The mixture may further include an additive.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
  • Semiconductor package and method of forming the same
    Patent number: 11456280
    Abstract: A semiconductor package includes a first die, a second die, a molding compound and a redistribution structure. The first die has a first conductive pillar and a first complex compound sheath surrounding and covering a sidewall of the first conductive pillar. The second die has a second conductive pillar and a protection layer laterally surrounding the second conductive pillar. The molding compound laterally surrounds and wraps around the first and second dies, and is in contact with the first complex compound sheath of the first die. The redistribution structure is disposed on the first and second dies and the molding compound.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: September 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Hung-Chun Cho
  • Integrated Circuit Package and Method
    Publication number: 20220302066
    Abstract: In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 22, 2022
    Inventors: Hung-Chun Cho, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR
    Publication number: 20220299880
    Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.
    Type: Application
    Filed: June 1, 2022
    Publication date: September 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang
  • Semiconductor Device and Methods of Manufacture
    Publication number: 20220302065
    Abstract: In an embodiment, a method includes forming a conductive feature adjacent to a substrate; treating the conductive feature with a protective material, the protective material comprising an inorganic core with an organic coating around the inorganic core, the treating the conductive feature comprising forming a protective layer over the conductive feature; and forming an encapsulant around the conductive feature and the protective layer. In another embodiment, the method further includes, before forming the encapsulant, rinsing the protective layer with water. In another embodiment, the protective layer is selectively formed over the conductive feature.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Fan-Out Interconnect Structure and Methods Forming the Same
    Publication number: 20220301919
    Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Yu-Hsiang HU, Chung-Shi LIU, Hung-Jui KUO, Ming-Da CHENG
  • Semiconductor device and method of fabricating the same
    Patent number: 11450603
    Abstract: A semiconductor device including a semiconductor die, an encapsulant and a redistribution structure is provided. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the semiconductor die and the encapsulant and is electrically connected to the semiconductor die. The redistribution structure includes a dielectric layer, a conductive via in the dielectric layer and a redistribution wiring covering the conductive via and a portion of the dielectric layer. The conductive via includes a pillar portion embedded in the dielectric layer and a protruding portion protruding from the pillar portion, wherein the protruding portion has a tapered sidewall.
    Type: Grant
    Filed: May 17, 2020
    Date of Patent: September 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sih-Hao Liao, Hung-Jui Kuo, Yu-Hsiang Hu
  • Method of fabricating package structure
    Patent number: 11450641
    Abstract: Provided is a method for forming a conductive feature including forming a seed layer over a substrate; forming a patterned mask layer on the seed layer, wherein the patterned mask layer has an opening exposing the seed layer; forming a conductive material in the opening; removing the patterned mask layer to expose a portion of the seed layer; and removing the portion of the seed layer by using an etching solution including a protective agent, thereby forming a conductive feature, wherein the protective agent has multiple active sites to adsorb on the conductive material.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: September 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chia-Wei Wang, Yu-Tzu Chang
  • Dense redistribution layers in semiconductor packages and methods of forming the same
    Patent number: 11417604
    Abstract: A method embodiment includes forming a patterned first photo resist over a seed layer. A first opening in the patterned first photo resist exposes the seed layer. The method further includes plating a first conductive material in the first opening on the seed layer, removing the patterned first photo resist, and after removing the patterned first photo resist, forming a patterned second photo resist over the first conductive material. A second opening in the patterned second photo resist exposes a portion of the first conductive material. The method further includes plating a second conductive material in the second opening on the first conductive material, removing the patterned second photo resist, and after removing the patterned second photo resist, depositing a dielectric layer around the first conductive material and the second conductive material.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Hung-Jui Kuo, Hui-Jung Tsai
  • Package structure and method of manufacturing the same
    Patent number: 11417582
    Abstract: A package structure includes a semiconductor die, an insulating encapsulation, a first redistribution circuit structure and a surface-modifying film. The semiconductor die has conductive terminals. The insulating encapsulation laterally encapsulates the semiconductor die and exposes the conductive terminals. The first redistribution circuit structure is located over the insulating encapsulation and electrically connected to the semiconductor die. The surface-modifying film is located on the insulating encapsulation and has a plurality of openings exposing edges of the conductive terminals, wherein the surface-modifying film separates the first redistribution circuit structure from the insulating encapsulation.
    Type: Grant
    Filed: August 30, 2020
    Date of Patent: August 16, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Hung-Chun Cho
  • CHIP PACKAGE AND METHOD OF FORMING THE SAME
    Publication number: 20220254724
    Abstract: A chip package includes a semiconductor die laterally encapsulating by an insulating encapsulant, a first dielectric portion, conductive vias, conductive traces and a second dielectric portion. The first dielectric portion covers the semiconductor die and the encapsulant. The conductive vias penetrate through the first dielectric portion and electrically connected to the semiconductor die. The conductive traces are disposed on the first dielectric portion. The second dielectric portion is disposed on the first dielectric portion and covering the conductive traces, wherein a first minimum lateral width of a conductive trace among the conductive traces is smaller than a second minimum lateral width of a conductive via among the conductive vias. A method of forming the chip package is also provided.
    Type: Application
    Filed: April 27, 2022
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Chen-Hua Yu, Hung-Jui Kuo
  • Via structure for packaging and a method of forming
    Patent number: 11410953
    Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Che Ho, Yi-Wen Wu, Chien Ling Hwang, Hung-Jui Kuo, Chung-Shi Liu
  • Method of making an integrated circuit package including an integrated circuit die soldered to a bond pad of a carrier
    Patent number: 11410918
    Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Hung-Jui Kuo, Ming-Che Ho, Tzung-Hui Lee
  • METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE
    Publication number: 20220246435
    Abstract: A method of manufacturing a semiconductor structure includes receiving a die comprising a top surface and a sacrificial layer covering the top surface; disposing a molding surrounding the die; removing the sacrificial layer from the die; disposing a polymer over the die and the molding, wherein the polymer has a first bottom surface contacting the die and a second bottom surface contacting the molding, and the first bottom surface is at a level substantially same as the second bottom surface.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Inventors: YU-HSIANG HU, WEI-YU CHEN, HUNG-JUI KUO, WEI-HUNG LIN, MING-DA CHENG, CHUNG-SHI LIU
  • Package structure comprising buffer layer for reducing thermal stress and method of forming the same
    Patent number: 11404342
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao
  • Semiconductor package and method
    Patent number: 11404308
    Abstract: In an embodiment, a method includes: forming a first dielectric layer over a die, the first dielectric layer including a photo-sensitive material; curing the first dielectric layer to reduce photo-sensitivity of the first dielectric layer; patterning the first dielectric layer by etching to form a first opening; forming a first metallization pattern in the first opening of the first dielectric layer; forming a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer including the photo-sensitive material; patterning the second dielectric layer by exposure and development to form a second opening; and forming a second metallization pattern in the second opening of the second dielectric layer, the second metallization pattern electrically connected to the first metallization pattern.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai
  • ALIGNMENT HOLDER AND TESTING APPARATUS
    Publication number: 20220238364
    Abstract: An alignment holder for holding a composite specimen includes a holder body and a positioning mechanism. The holder body is configured to clamp a first side of the composite specimen therein. The positioning mechanism is movably engaged with the holder body. The positioning mechanism is configured to lean against a second side of the composite specimen and move relatively to the holder body for adjusting a clamping position of the composite specimen clamped by the holder body.
    Type: Application
    Filed: April 13, 2022
    Publication date: July 28, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Wang, Hung-Jui Kuo, Hui-Jung Tsai
  • Package structure and method of fabricating the same
    Patent number: 11398416
    Abstract: A structure including a semiconductor die, a conductive pillar, and an insulating encapsulation is provided. The conductive pillar includes a first pillar portion and a second pillar portion disposed on the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion. The insulating encapsulation laterally encapsulates the semiconductor die and the conductive pillar.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzung-Hui Lee, Hung-Jui Kuo, Ming-Che Ho
  • PACKAGE
    Publication number: 20220230980
    Abstract: A package includes a die and a redistribution layer. A top surface of the die has a first area and a second area connected with the first area. The redistribution layer structure includes a first insulation layer, a redistribution layer, and a second insulation layer. The first insulation layer is overlapping with the second area. The redistribution layer is disposed above the die. The second insulation layer is disposed above the redistribution layer and overlapping with the second area and the first area. The second insulation layer covers a top surface of the first insulation layer and is in contact with a side surface of the first insulation layer and the top surface of the die.
    Type: Application
    Filed: January 21, 2021
    Publication date: July 21, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tian Hu, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao