Patents by Inventor Hung-Kun LO

Hung-Kun LO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250253277
    Abstract: A semiconductor device includes a substrate, a routing structure, a device layer and a bonding layer. The routing structure is disposed over the substrate, and includes a plurality of dielectric layer and a plurality of conductive features. The device layer is disposed over the routing structure. The bonding layer is disposed between the substrate and the routing structure, wherein the bonding layer includes a plurality of microchannels.
    Type: Application
    Filed: February 4, 2024
    Publication date: August 7, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Kun Lo, Wei-Yen Woon
  • Publication number: 20250125213
    Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a first substrate with a first surface having a normal direction along a first direction; a first IC chip bonded to the first substrate; and a second IC chip electrically connected to the first IC chip. The first and second IC chips are sealed in a same package having a sealing material layer, and the sealing material layer includes a first anisotropic thermal dissipation material. The first anisotropic thermal dissipation material is thermally conductive with a first thermal conductivity along the first direction and a second thermal conductivity along a second direction being perpendicular to the first direction. The second thermal conductivity is substantially greater than the first thermal conductivity.
    Type: Application
    Filed: February 27, 2024
    Publication date: April 17, 2025
    Inventor: Hung-Kun LO
  • Publication number: 20250089360
    Abstract: A method includes forming a fin structure over a bottom dielectric isolator and a substrate. The fin structure includes a bottom channel layer, a sacrificial layer over the bottom channel layer, and a top channel layer over the sacrificial layer. A dummy gate is formed across the fin structure. Portions of the fin structure not covered by the gate structure are removed to expose a top surface of the bottom dielectric isolator. First source/drain epitaxial structures are epitaxially grown over the bottom dielectric isolator and are connected to the bottom channel layer. Second source/drain epitaxial structures are epitaxially grown over the first source/drain epitaxial structures and are connected to the top channel layer. The dummy gate and the sacrificial layer are replaced with a gate structure.
    Type: Application
    Filed: September 12, 2023
    Publication date: March 13, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao-Ming LIEN, Wei-Yen WOON, Hung-Kun LO