Abstract: A manufacturing method of a split gate trench device includes forming an epitaxial layer on a substrate, and forming a trench in the epitaxial layer, wherein the trench is divided into a first part and a second part above the first part. A shielding gate and a shielding oxide layer are then formed in the first part, wherein the shielding oxide layer is located between the shielding gate and the trench and exposes the second part. The second part is filled with an oxide, two grooves having a contour that is wide at the top and narrow at the bottom are then formed in the oxide, and a part of a sidewall of the trench is exposed. A gate oxide layer is formed on an exposed surface of the sidewall, and a first top gate and a second top gate are then formed in each of the two grooves.

Abstract: A split gate trench device, including a substrate, an epitaxial layer having a trench, and a split gate structure, is provided. The epitaxial layer is formed on the substrate, and the split gate structure is disposed in the trench. The split gate structure includes a shielding gate, two top gates, a shielding oxide layer, a gate oxide layer, and an inter-gate oxide layer. Each of the two top gates has a shape that is wide at the top and narrow at the bottom.

Abstract: A manufacturing method of a split gate trench device includes forming an epitaxial layer on a substrate, and forming a trench in the epitaxial layer, wherein the trench is divided into a first part and a second part above the first part. A shielding gate and a shielding oxide layer are then formed in the first part, wherein the shielding oxide layer is located between the shielding gate and the trench and exposes the second part. The second part is filled with an oxide, two grooves having a contour that is wide at the top and narrow at the bottom are then formed in the oxide, and a part of a sidewall of the trench is exposed. A gate oxide layer is formed on an exposed surface of the sidewall, and a first top gate and a second top gate are then formed in each of the two grooves.

Abstract: A gallium nitride high electron mobility transistor including a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a gate electrode, a source electrode, at least one first p-type gallium nitride island, a drain electrode, and a dielectric layer is provided. A second side of the gate electrode is opposite to a first side of the gate electrode. The first p-type gallium nitride island is disposed on the barrier layer on the second side of the gate electrode, and the drain electrode is also disposed on the barrier layer on the second side of the gate electrode and covers the first p-type gallium nitride island. The dielectric layer is disposed between the drain electrode and the first p-type gallium nitride island, so that the first p-type gallium nitride island is electrically floating.

Abstract: A gallium nitride high electron mobility transistor including a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a gate electrode, a source electrode, a drain electrode, and multiple first p-type gallium nitride islands is provided. A second side of the gate electrode is opposite to a first side of the gate electrode. The first p-type gallium nitride islands are respectively disposed between a first side of the drain electrode and the second side of the gate electrode, and the first p-type gallium nitride islands are electrically floating.

Abstract: A gate structure for gallium nitride (GaN) high electron mobility transistor (HEMT) includes a heterogeneous structure, a doped GaN layer, an insulating layer, an undoped GaN layer, and a gate metal layer. The heterogeneous structure includes a channel layer and a barrier layer on the channel layer. The doped GaN layer is disposed on the barrier layer, the insulating layer is disposed on both sides of the top portion of the doped GaN layer, and the undoped GaN layer is disposed between the doped GaN layer and the insulating layer. The gate metal layer is disposed on the doped GaN layer and covers the insulating layer and the undoped GaN layer. The undoped GaN layer can protect the underlying doped GaN layer, and the insulating layer has the effect of preventing gate leakage.

Abstract: A method of manufacturing a gate structure for gallium nitride (GaN) high electron mobility transistor (HEMT) includes orderly forming a channel layer, a barrier layer, a doped GaN layer, an undoped GaN layer, and an insulating layer on a substrate, and then removing a portion of the insulating layer to form a trench. A gate metal layer is formed on the substrate to cover the insulating layer and the trench, and then a mask layer aligned with the trench is formed on the gate metal layer, wherein the mask layer partially overlaps the insulating layer. By using the mask layer as an etching mask, the exposed gate metal layer and the underlying insulating layer, the undoped GaN layer and the doped GaN layer are removed, and then the mask layer is removed.

Abstract: A method of manufacturing a gate structure for gallium nitride (GaN) high electron mobility transistor (HEMT) includes orderly forming a channel layer, a barrier layer, a doped GaN layer, an undoped GaN layer, and an insulating layer on a substrate, and then removing a portion of the insulating layer to form a trench. A gate metal layer is formed on the substrate to cover the insulating layer and the trench, and then a mask layer aligned with the trench is formed on the gate metal layer, wherein the mask layer partially overlaps the insulating layer. By using the mask layer as an etching mask, the exposed gate metal layer and the underlying insulating layer, the undoped GaN layer and the doped GaN layer are removed, and then the mask layer is removed.

Abstract: A gate structure for gallium nitride (GaN) high electron mobility transistor (HEMT) includes a heterogeneous structure, a doped GaN layer, an insulating layer, an undoped GaN layer, and a gate metal layer. The heterogeneous structure includes a channel layer and a barrier layer on the channel layer. The doped GaN layer is disposed on the barrier layer, the insulating layer is disposed on both sides of the top portion of the doped GaN layer, and the undoped GaN layer is disposed between the doped GaN layer and the insulating layer. The gate metal layer is disposed on the doped GaN layer and covers the insulating layer and the undoped GaN layer. The undoped GaN layer can protect the underlying doped GaN layer, and the insulating layer has the effect of preventing gate leakage.