Patents by Inventor Hung Lee
Hung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240186258Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. An alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. The first semiconductor workpiece is bonded to the second semiconductor workpiece. A shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. A layer of an integrated circuit (IC) structure is formed over the second semiconductor workpiece based at least in part on the shift value.Type: ApplicationFiled: January 24, 2024Publication date: June 6, 2024Inventors: Yeong-Jyh Lin, Ching I Li, De-Yang Chiou, Sz-Fan Chen, Han-Jui Hu, Ching-Hung Wang, Ru-Liang Lee, Chung-Yi Yu
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Publication number: 20240186400Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.Type: ApplicationFiled: February 13, 2024Publication date: June 6, 2024Inventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
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Publication number: 20240182754Abstract: The present invention relates to an adhesive for a stoma and an adhesive tape for a stoma comprising the same. Specifically, the present invention relates to: an adhesive for a stoma, which can be attached to an affected part, having high adhesion, and has improved functionality for easy detachment from the skin; and an adhesive tape for a stoma comprising the same.Type: ApplicationFiled: February 28, 2022Publication date: June 6, 2024Applicant: Korea Institute of Science and TechnologyInventors: Hosung KONG, Hung Gu HAN, Sook LEE, Edward SH KIM
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Publication number: 20240180451Abstract: Systems, methods, and apparatuses for enabling a plurality of non-invasive, physiological sensors to obtain physiological measurements from essentially the same, overlapping, or proximate regions of tissue of a patient are disclosed. Each of a plurality of sensors can be integrated with or attached to a multi-sensor apparatus and can be oriented such that each sensor is directed towards, or can obtain a measurement from, the same or a similar location.Type: ApplicationFiled: October 25, 2023Publication date: June 6, 2024Inventors: Mohamed K. Diab, Kevin Hughes Pauley, Jesse Chen, Cristiano Dalvi, Hung The Vo, Ferdyan Lesmana, Jeroen Poeze, Ruiqi Long, Venkatramanan Krishnamani, Frank Lee
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Patent number: 12002675Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate and forming a dehydrated film over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form an exposed portion and an unexposed portion of the photoresist layer. The photoresist layer is developed to remove the unexposed portion of the photoresist layer and a first portion of the dehydrated film over the unexposed portion of the photoresist layer. In an embodiment, the method includes etching the substrate by using the exposed portion of the photoresist layer as a mask.Type: GrantFiled: January 22, 2021Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Yu Chen, Chih-Cheng Liu, Yi-Chen Kuo, Jr-Hung Li, Tze-Liang Lee, Ming-Hui Weng, Yahru Cheng
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Patent number: 12001142Abstract: The present application relates to a wafer processing device and a wafer processing method. The wafer processing device includes: a spraying unit configured to spray a photoresist-removing solution to remove a photoresist; and a heating unit mounted to the spraying unit and configured to heat the photoresist-removing solution to a preset temperature. According to the wafer processing device and wafer processing method of the present application, the photoresist-removing solution is heated to a preset temperature, so that the photoresist-removing solution dissolves the photoresist more rapidly and thoroughly. Therefore, the photoresist may be removed from a surface of the wafer more thoroughly, and further a yield of the wafer is increased.Type: GrantFiled: March 10, 2021Date of Patent: June 4, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Shih-Hung Lee
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Publication number: 20240178095Abstract: A semiconductor device includes a substrate, a first device, a second device, a ring structure, a lid structure, and a first adhesive layer. The first device is disposed on the substrate. The second device is adjacent to the first device and is disposed on the substrate. The ring structure is disposed over the substrate and the second device. The ring structure includes a cover and a leg extending out from the cover. The cover has a through opening. The lid structure is disposed over the ring structure and the first device. The lid structure includes a body and a protrusion protruding from the body. The protrusion of the lid structure is inserted into the through opening of the cover of the ring structure. The first adhesive layer is disposed between the body of the lid structure and the cover of the ring structure and includes phase change thermal interface material.Type: ApplicationFiled: February 10, 2023Publication date: May 30, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wensen Hung, Tsung-Yu Chen, Meng-Tsan Lee
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Publication number: 20240174779Abstract: A resin composition is provided. The resin composition includes a resin mixture, a flame retardant, a spherical silica and a siloxane coupling agent. The resin mixture includes a first resin polymerized by a monomer mixture including styrene, divinylbenzene and ethylene, a second resin including a polyphenylene ether resin modified by bismaleimide, and a SBS resin. The resin composition of the present disclosure can have a high glass transition temperature, a low dielectric constant and a low dissipation factor.Type: ApplicationFiled: January 3, 2023Publication date: May 30, 2024Applicant: NAN YA PLASTICS CORPORATIONInventors: Te-Chao Liao, Wei-Ru Huang, Hung-Yi Chang, Chia-Lin Liu, HungFan Lee
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Publication number: 20240175317Abstract: A blind lifting control module includes a transmitting wheel, an anti-backward unit and a driving unit disposed to a supporting unit. The transmitting wheel for connecting a blind reeled horizontal axle has a wheel ratchet portion meshable with a corresponding reel ratchet portion of a driving reel of the driving unit. The anti-backward unit has a torsion spring operable and deformable relative to the transmitting wheel. A pull cord is reeled on the driving reel and has a free end passing through a thrust member and a hindering member, and is pulled to shift the torsion spring to a released state to permit lowering of a blind. The thrust member is turned by pulling of the pull cord to thrust the driving reel to mesh with the transmitting wheel for lifting the blind.Type: ApplicationFiled: February 6, 2024Publication date: May 30, 2024Inventors: Cheng-Hung LEE, Lung-Yi CHIANG
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Publication number: 20240170473Abstract: A chip package structure including a heat dissipation base, a first redistribution layer, a second redistribution layer, at least one chip, at least one metal stack, a plurality of conductive structures, and an encapsulant is provided. The second redistribution layer is disposed on the heat dissipation base and thermally coupled to the heat dissipation base. The chip, the metal stack, and the conductive structures are disposed between the second redistribution layer and the first redistribution layer. An active surface of the chip is electrically connected to the first redistribution layer and an inactive surface of the chip is thermally coupled to the second redistribution layer via the metal stack. The first redistribution layer is electrically connected to the second redistribution layer via the conductive structures. The encapsulant is filled between the second redistribution layer and the first redistribution layer. A manufacturing method of a chip package structure is also provided.Type: ApplicationFiled: July 6, 2023Publication date: May 23, 2024Applicant: Industrial Technology Research InstituteInventors: Hao-Che Kao, Wen-Hung Liu, Yu-Min Lin, Ching-Kuan Lee
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Publication number: 20240170314Abstract: A display device manufacturing apparatus includes a working platform, a transferring station including a transferring gantry and a transferring welding device, a defect inspecting station including an inspecting gantry and a defect inspecting device, and a mending station including a mending gantry and a mending device. The working platform includes a plurality of pairs of conveying paths, and a plurality of carriers disposed on the plurality of pairs of conveying paths. The transferring gantry, inspecting gantry and mending gantry are disposed on the working platform and stride over the conveying paths.Type: ApplicationFiled: November 15, 2023Publication date: May 23, 2024Inventors: TSAN-JEN CHEN, WEN-I LEE, TZU-HUNG HSU, QING-FENG PAN
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Publication number: 20240170059Abstract: A method of operating a memory cell includes the following steps. A first plurality of bias operations is performed to the memory cell using a first voltage, wherein the memory cell comprises a variable resistance pattern, and the first voltage of each cycle of the first plurality of bias operations has a same first polarity. The memory cell is determined whether reaches a fatigue threshold. After the determination determines that the memory cell reaches the fatigue threshold, a second plurality of bias operations is performed to the memory cell using a second voltage, wherein the second voltage of each cycle of the second plurality of bias operations has a same second polarity, and the second polarity is opposite to the first polarity.Type: ApplicationFiled: March 28, 2023Publication date: May 23, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY, National Taiwan Normal UniversityInventors: Kuo-Yu HSIANG, Min-Hung LEE
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Publication number: 20240172475Abstract: The invention discloses an etching solution and a manufacturing method of a display panel. The method includes following steps: providing a first substrate; forming a conductive layer stack including a first sub-layer, a second sub-layer and a third sub-layer, each of the first sub-layer and the second sub-layer includes a transparent conductive material including indium-containing oxide, the third sub-layer is disposed between the first sub-layer and the second sub-layer, and the third sub-layer includes silver or silver alloy; performing an etching process, an etching solution is used to etch the first sub-layer, the second sub-layer and the third sub-layer to form a first patterned sub-layer, a second patterned sub-layer and a third patterned sub-layer, and the etching solution includes 1 to 2.6 wt % of nitric acid, 35 to 45 wt % of acetic acid, 35 to 45 wt % of phosphoric acid and a remaining amount of water.Type: ApplicationFiled: October 17, 2023Publication date: May 23, 2024Applicant: HANNSTAR DISPLAY CORPORATIONInventors: Li-Fang Chiu, Ching-Chieh Lee, Chien-Hung Wu
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Publication number: 20240170053Abstract: A latch formed from a memory cell includes a clock input terminal configured to receive a clock signal, complementary first and second data terminals, and a latch circuit. The latch circuit has first and second inverters. The first inverter has an input terminal coupled to the first data terminal, and the second inverter has an input terminal coupled to the second data terminal. A first pass gate transistor is coupled between an output terminal of the second inverter and the first data terminal. A second pass gate transistor is coupled between an output terminal of the first inverter and the second data terminal. The first and second pass gate transistors each have a gate terminal coupled to the clock input terminal. The input terminal of the first inverter is not directly connected to the output terminal of the second inverter, and the input terminal of the second inverter is not directly connected to the output terminal of the first inverter.Type: ApplicationFiled: January 26, 2024Publication date: May 23, 2024Inventors: Hua-Hsin Yu, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh
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Patent number: 11987566Abstract: The present invention provides a novel compound for effectively preventing nerve damage and protecting nerves, and a preparation method thereof. Besides, the present invention also provides a pharmaceutical composition comprising the novel compound, and a use of the novel compound for preventing nerve damage and protecting nerves.Type: GrantFiled: January 28, 2022Date of Patent: May 21, 2024Assignee: GENHEALTH PHARMA CO., LTD.Inventors: Lain-Tze Lee, Hui-Ping Tsai, Yi-Wen Lin, Shu-Fen Huang, Shih-Hung Liu, Chin-Wei Liu, Pi-Tsan Huang, Mei-Hui Chen
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Publication number: 20240161822Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.Type: ApplicationFiled: January 19, 2024Publication date: May 16, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-jer Hsieh, Yu-Hao Hsu, Zhi-Hao Chang, Cheng Hung Lee
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Patent number: 11984485Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.Type: GrantFiled: March 3, 2022Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hsien Cheng, Jr-Hung Li, Tai-Chun Huang, Tze-Liang Lee, Chung-Ting Ko, Jr-Yu Chen, Wan-Chen Hsieh
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Patent number: 11984516Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.Type: GrantFiled: February 16, 2023Date of Patent: May 14, 2024Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.Inventors: Fu-Chou Liu, Jui-Hung Hsu, Yu-Chiang Peng, Chien-Chen Lee, Ya-Han Chang, Li-Chun Hung
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Patent number: 11978511Abstract: A phase-change memory (PCM) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. The phase-change feature is configured to change its data state based on a write operation performed on the PCM cell. The write operation includes a reset stage and a set stage. In the reset stage, a plurality of reset current pulses are applied to the PCM cell, and the reset current pulses have increasing current amplitudes. In the set stage, a plurality of set current pulses are applied to the PCM cell, and the set current pulses exhibit an increasing trend in current amplitude. The current amplitudes of the set current pulses are smaller than those of the reset current pulses.Type: GrantFiled: January 21, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Huei Lee, Chun-Wei Chang, Jian-Hong Lin, Wen-Hsien Kuo, Pei-Chun Liao, Chih-Hung Nien
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Patent number: D1026916Type: GrantFiled: January 5, 2022Date of Patent: May 14, 2024Assignee: COMPAL ELECTRONICS, INC.Inventors: Hao-Jen Fang, Kung-Ju Chen, Wei-Yi Chang, Chun-Chieh Chen, Chih-Wen Chiang, Sheng-Hung Lee