Patents by Inventor Hung Li

Hung Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11341018
    Abstract: A method for detecting abnormality adapted to detect abnormal operations of an operating system is provided. The method includes: calculating a safe range of usage of the operating system during one or more time periods according to a historical data stream; calculating abnormal ratios corresponding to the one or more time periods according to a current data stream and the safe range of usage; selecting one or more abnormal time periods from the one or more time periods according to a threshold and the abnormal ratios; calculating an abnormal indicator for each of the one or more abnormal time periods according to the historical data stream and the current data stream; and ranking the one or more abnormal time periods according to the abnormal indicator(s).
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: May 24, 2022
    Assignee: Acer Cyber Security Incorporated
    Inventors: Chun-Hsien Li, Chien-Hung Li, Jun-Mein Wu, Ming-Kung Sun, Zong-Cyuan Jhang, Yin-Hsong Hsu, Chiung-Ying Huang, Tsung-Hsien Tsai
  • Patent number: 11342015
    Abstract: A memory device and a memory circuit is provided. The memory device includes a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ), a read word line, a selector and a write word line. The MTJ stands on the SOT layer. The read word line is electrically connected to the MTJ. The write word line is connected to the SOT layer through the selector. The write word line is electrically connected to the SOT layer when the selector is turned on, and the write word line is electrically isolated from the SOT layer when the selector is in an off state.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Chung-Te Lin, Shy-Jay Lin, Tzu-Chiang Chen, Ming-Yuan Song, Hon-Sum Philip Wong
  • Patent number: 11340204
    Abstract: A system and a method for managing and trading fresh foods according to a flavor thereof, comprising a plurality of fresh foods, an image capturing module, a processing module and a classification module. The fresh food is attached with a product label including a code and a colorimetric transducer array that comprises at least one sensing material for sensing the fresh food. The sensing material undergoes a chemical reaction with at least one metabolic molecule of the fresh food to change the sensing material from an initial color to an indication color. The image capturing module captures an image comprising an appearance of the fresh food, the code and the indication color. The processing module provides a real-time information according to a comparison result between the image and a database. The classification module receives the real-time information and classifies the fresh food according to the real-time information.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: May 24, 2022
    Assignee: TAIWAN CARBON NANO TECHNOLOGY CORPORATION
    Inventors: Ching-Tung Hsu, Chun-Wei Shih, Chao-Chieh Lin, Yuan-Shin Huang, Chia-Hung Li, Chun-Hsien Tsai, Chun-Jung Tsai
  • Patent number: 11342380
    Abstract: A memory device includes a memory cell, a selector layer and a first work function metal layer. The selector layer is disposed between a first electrode and a second electrode over the memory cell. The first work function metal layer is disposed between the selector layer and the first electrode.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jung-Piao Chiu, Tzu-Chiang Chen, Yu-Sheng Chen, Xinyu Bao
  • Publication number: 20220157938
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.
    Type: Application
    Filed: February 7, 2022
    Publication date: May 19, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Kuo-Hua PAN, Jhon-Jhy LIAW, Chao-Ching CHENG, Hung-Li CHIANG, Shih-Syuan HUANG, Tzu-Chiang CHEN, I-Sheng CHEN, Sai-Hooi YEONG
  • Patent number: 11337318
    Abstract: An information handling system may include a chassis and a variable venting assembly comprising a wall having a plurality of spaced venting holes and an adjustable venting block mechanically coupled to the wall via an axis of rotation and having a plurality of spaced blocking fins such that as a position of the adjustable venting block varies, an overlap between the spaced blocking fins and the spaced venting holes varies.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: May 17, 2022
    Assignee: Dell Products L.P.
    Inventors: Yen-Lin Wang, Chao-Hung Li, Jen-Chun Hsueh
  • Patent number: 11335604
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a lower fin structure and an upper fin structure disposed over the lower fin structure is formed. The upper fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The first semiconductor layers are partially etched to reduce widths of the first semiconductor layers. An oxide layer is formed over the upper fin structure. A sacrificial gate structure is formed over the upper fin structure with the oxide layer. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed to form a gate space. The oxide layer is removed to expose the second semiconductor layers in the gate space. A gate structure is formed around the second semiconductor layers in the gate space.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, I-Sheng Chen, Hung-Li Chiang, Tzu-Chiang Chen, Kai-Tai Chang
  • Publication number: 20220141973
    Abstract: An information handling system may include a chassis and a variable venting assembly comprising a wall having a plurality of spaced venting holes and an adjustable venting block mechanically coupled to the wall via an axis of rotation and having a plurality of spaced blocking fins such that as a position of the adjustable venting block varies, an overlap between the spaced blocking fins and the spaced venting holes varies.
    Type: Application
    Filed: November 3, 2020
    Publication date: May 5, 2022
    Applicant: Dell Products L.P.
    Inventors: Yen-Lin WANG, Chao-Hung LI, Jen-Chun HSUEH
  • Publication number: 20220140098
    Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.
    Type: Application
    Filed: June 18, 2021
    Publication date: May 5, 2022
    Inventors: Chao-Ching Cheng, Yi-Tse Hung, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li, Jin Cai
  • Patent number: 11318170
    Abstract: The invention relates to the treatment of chronic stroke, traumatic brain injury, and neurodegenerative disorders using umbilical cord blood cells.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: May 3, 2022
    Assignee: StemCyte, Inc.
    Inventors: Shinn-Zong Lin, Woei-Cherng Shyu, Hung Li
  • Publication number: 20220131267
    Abstract: An antenna structure includes a metal mechanism element, a ground element, a feeding radiation element, and a dielectric substrate. The metal mechanism element has a slot. The slot has a first closed end and a second closed end. The ground element is coupled to the metal mechanism element. The feeding radiation element has a feeding point. The feeding radiation element is coupled to the ground element. The dielectric substrate has a first surface and a second surface which are opposite to each other. The feeding radiation element is disposed on the first surface of the dielectric substrate. The second surface of the dielectric substrate is adjacent to the metal mechanism element. The slot of the metal mechanism element is excited to generate a first frequency band and a second frequency band. The feeding radiation element is excited to generate a third frequency band.
    Type: Application
    Filed: July 8, 2021
    Publication date: April 28, 2022
    Inventors: Po-Yen CHEN, Kuan-Hung LI
  • Publication number: 20220131219
    Abstract: Battery packs according to some embodiments of the present technology may include a longitudinal beam. The packs may include a plurality of battery cells disposed adjacent the longitudinal beam. Each battery cell may be characterized by a first surface, and a second surface opposite the first surface. Each battery cell may be characterized by a third surface extending vertically between the first surface and the second surface. The first surface may face the longitudinal beam, and battery terminals may extend from the third surface. Each battery cell may be characterized by a fourth surface opposite the third surface. The packs may include a lid coupled with the first surface of each battery cell of the plurality of battery cells. The packs may include a base coupled with the second surface of each battery cell of the plurality of battery cells.
    Type: Application
    Filed: May 11, 2021
    Publication date: April 28, 2022
    Inventors: Nivay Anandarajah, Evan D. Maley, Alexander J. Clarabut, Yu-Hung Li, John M. Schoech
  • Publication number: 20220130008
    Abstract: There is provided a method for embedding a digital watermark into and extracting a digital watermark from a numerical data set. In accordance with embodiments of the present disclosure, there is provided a method for embedding a digital watermark into a numerical data set. The method includes selecting portions of the numerical data set identified as data noise, the selected portions to be used for embedding the digital watermark into the numerical data set, the digital watermark being unique for each recipient of the numerical data. The method further includes replacing the least significant bit (LSB) of at least some of the selected portions of the numerical data set with at least portion of the digital watermark.
    Type: Application
    Filed: October 22, 2020
    Publication date: April 28, 2022
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Roozbeh JALALI, Haolin GUO, Michael Chih Hung LI, Zanqing ZHANG
  • Publication number: 20220131117
    Abstract: Battery packs according to some embodiments of the present technology may include a longitudinal beam. The packs may include a plurality of battery cells disposed adjacent the longitudinal beam. Each battery cell may be characterized by a first surface, and a second surface opposite the first surface. Each battery cell may be characterized by a third surface extending vertically between the first surface and the second surface. The first surface may face the longitudinal beam, and battery terminals may extend from the third surface. Each battery cell may be characterized by a fourth surface opposite the third surface. The packs may include a lid coupled with the first surface of each battery cell of the plurality of battery cells. The packs may include a base coupled with the second surface of each battery cell of the plurality of battery cells.
    Type: Application
    Filed: October 22, 2020
    Publication date: April 28, 2022
    Inventors: Nivay Anandarajah, Evan D. Maley, Alexander J. Clarabut, Yu-Hung Li, John M. Schoech
  • Publication number: 20220131011
    Abstract: A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, Chun-Chieh Lu, Hung-Li Chiang, Tzu-Chiang Chen
  • Publication number: 20220131222
    Abstract: Battery packs according to some embodiments of the present technology may include a longitudinal beam. The packs may include a plurality of battery cells disposed adjacent the longitudinal beam. Each battery cell may be characterized by a first surface, and a second surface opposite the first surface. Each battery cell may be characterized by a third surface extending vertically between the first surface and the second surface. The first surface may face the longitudinal beam, and battery terminals may extend from the third surface. Each battery cell may be characterized by a fourth surface opposite the third surface. The packs may include a lid coupled with the first surface of each battery cell of the plurality of battery cells. The packs may include a base coupled with the second surface of each battery cell of the plurality of battery cells.
    Type: Application
    Filed: May 12, 2021
    Publication date: April 28, 2022
    Inventors: Nivay Anandarajah, Evan D. Maley, Alexander J. Clarabut, Yu-Hung Li, John M. Schoech
  • Publication number: 20220131221
    Abstract: Battery packs according to some embodiments of the present technology may include a longitudinal beam. The packs may include a plurality of battery cells disposed adjacent the longitudinal beam. Each battery cell may be characterized by a first surface, and a second surface opposite the first surface. Each battery cell may be characterized by a third surface extending vertically between the first surface and the second surface. The first surface may face the longitudinal beam, and battery terminals may extend from the third surface. Each battery cell may be characterized by a fourth surface opposite the third surface. The packs may include a lid coupled with the first surface of each battery cell of the plurality of battery cells. The packs may include a base coupled with the second surface of each battery cell of the plurality of battery cells.
    Type: Application
    Filed: May 12, 2021
    Publication date: April 28, 2022
    Inventors: Nivay Anandarajah, Evan D. Maley, Alexander J. Clarabut, Yu-Hung Li, John M. Schoech
  • Publication number: 20220131220
    Abstract: Battery packs according to some embodiments of the present technology may include a longitudinal beam. The packs may include a plurality of battery cells disposed adjacent the longitudinal beam. Each battery cell may be characterized by a first surface, and a second surface opposite the first surface. Each battery cell may be characterized by a third surface extending vertically between the first surface and the second surface. The first surface may face the longitudinal beam, and battery terminals may extend from the third surface. Each battery cell may be characterized by a fourth surface opposite the third surface. The packs may include a lid coupled with the first surface of each battery cell of the plurality of battery cells. The packs may include a base coupled with the second surface of each battery cell of the plurality of battery cells.
    Type: Application
    Filed: May 12, 2021
    Publication date: April 28, 2022
    Inventors: Nivay Anandarajah, Evan D. Maley, Alexander J. Clarabut, Yu-Hung Li, John M. Schoech
  • Patent number: 11316047
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a gate structure over the substrate. The gate structure has a first sidewall. The method includes forming a spacer element over the first sidewall of the gate structure. The method includes forming a source/drain portion adjacent to the spacer element and the gate structure. The source/drain portion has a first top surface. The method includes depositing an etch stop layer over the first top surface of the source/drain portion. The etch stop layer is made of nitride. The method includes forming a dielectric layer over the etch stop layer. The dielectric layer has a second sidewall and a bottom surface, the etch stop layer is in direct contact with the bottom surface, and the spacer element is in direct contact with the second sidewall.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ting Ko, Bo-Cyuan Lu, Jr-Hung Li, Chi-On Chui
  • Publication number: 20220123115
    Abstract: A semiconductor device a method of forming the same are provided. A semiconductor device includes a gate stack over a substrate. A first dielectric layer is over the gate stack. The first dielectric layer includes a first material. A second dielectric layer is over the first dielectric layer. The second dielectric layer includes a second material different from the first material. A first conductive feature is adjacent the gate stack. A second conductive feature is over and in physical contact with a topmost surface of the first conductive feature. A bottommost surface of the second conductive feature is in physical contact with a topmost surface of the second dielectric layer.
    Type: Application
    Filed: March 5, 2021
    Publication date: April 21, 2022
    Inventors: Pei-Yu Chou, Jr-Hung Li, Tze-Liang Lee