Patents by Inventor Hung Li

Hung Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804268
    Abstract: A semiconductor device includes a substrate, a first source/drain structure, a vertical channel layer, a gate structure, a second source/drain structure and a body epitaxial layer. The first source/drain structure is over the substrate. The vertical channel layer is over the first source/drain structure. The gate structure is on a first sidewall of the vertical channel layer. The second source/drain structure is over the vertical channel layer. The body epitaxial layer is on a second sidewall of the vertical channel layer. The body epitaxial layer and the vertical channel layer are of opposite conductivity types, and the body epitaxial layer is separated from the gate structure.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, Szu-Wei Huang, Chih-Chieh Yeh, Yee-Chia Yeo
  • Patent number: 10797050
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a first gate structure formed over a fin structure, and a first capping layer formed over the first gate structure. The FinFET device structure includes a first etching stop layer formed over the first capping layer and the first gate structure, and a top surface and a sidewall surface of the first capping layer are in direct contact with the first etching stop layer.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
  • Patent number: 10789882
    Abstract: An optical compensation apparatus applied to panels is disclosed. A panel of the panels includes sub-pixels. The optical compensation apparatus includes an optical measurement module, a data processing module and an optical compensation module. The optical measurement module measures optical measurement values corresponding to the sub-pixels. The data processing module determines first optical compensation values needed for the sub-pixels according to the optical measurement values, determines an overall compensation operation reference of the panel accordingly, determines a demura algorithm suitable for the panel according to at least one threshold compensation value and the overall compensation operation reference and obtains second optical compensation values accordingly. Then, the optical compensation module outputs the second optical compensation values to perform optical compensation on a display data provided to the panel.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: September 29, 2020
    Assignee: Raydium Semiconductor Corporation
    Inventors: Shang-Ping Tang, Hung Li
  • Publication number: 20200300827
    Abstract: A gas-sensing tattoo sticker includes an adhesive layer, a coloring reaction layer, and a chemical reaction layer, disposed by stacking. The chemical reaction layer includes reaction zones capable of reacting with a gas to be tested to produce a chemical change; the coloring reaction layer includes coloring sides and correspondingly disposed reaction sides in contact with the reaction zones, and includes a coloring indicator to produce a coloring reaction corresponding to the chemical change of the reaction sides; to and the adhesive layer is provided on a side of the coloring reaction layer or the chemical reaction layer to provide adhesion, thereby completing the gas-sensing tattoo sticker, changes of gas in the surrounding environment can be sensed when air inlet sides are outwardly adhered on an object; and the smell of an object itself can be sensed when the air inlet sides are inwardly adhered on the object.
    Type: Application
    Filed: March 20, 2020
    Publication date: September 24, 2020
    Inventors: Ching-Tung HSU, Chun-Wei SHIH, Kuang-Che LEE, Chia-Hung LI, Chien-Yao HUANG, Chun-Hsien TSAI, Ting-Chuan LEE, Chun-Jung TSAI
  • Publication number: 20200302379
    Abstract: The invention provides a system for managing food information based on an odor, which comprises a gas sensing module, a processing module, a blockchain module and a display module. The gas sensing module includes a colorimetric gas sensing chip reacting with odor molecules emitted by the food to form a coloring reaction and present a color image corresponding to the food. The processing module includes a conversion unit for converting the color image into identification information corresponding to the food. The blockchain module includes a plurality of nodes, and the plurality of nodes store identification information corresponding to the food. The display module includes an identification label corresponding to the identification information. Therefore, when the invention is applied to the blockchain technology, it can remove the doubt that the data on the chain can be falsified before the data is uploaded.
    Type: Application
    Filed: March 20, 2020
    Publication date: September 24, 2020
    Inventors: Ching-Tung HSU, Chun-Wei SHIH, Kuang-Che LEE, Chia-Hung LI, Chien-Yao HUANG, Chun-Hsien TSAI, Ting-Chuan LEE, Chun-Jung TSAI
  • Publication number: 20200300774
    Abstract: The invention provides a system for evaluating food flavors based on a gas, including a multi-gas sensing module and an odor information processing module. The sensing module includes a colorimetric gas sensing chip for reacting with odor molecules emitted by the food to be evaluated to form a coloring reaction, and the sensing module generates a color image respectively corresponding to coloring reaction according to the coloring reaction. The processing module is communicatively connected with the sensing module and includes an image acquisition unit for converting the color image into an odor information, a database unit including a plurality of identification information, and an arithmetic unit perform a calculation to form a result for evaluating the food flavors based on the plurality of identification information and the color image. The user can judge the actual condition of foods according to the result for evaluating the food flavors.
    Type: Application
    Filed: March 20, 2020
    Publication date: September 24, 2020
    Inventors: Ching-Tung HSU, Chun-Wei SHIH, Kuang-Che LEE, Chia-Hung LI, Chien-Yao HUANG, Chun-Hsien TSAI, Ting-Chuan LEE, Chun-Jung TSAI
  • Publication number: 20200300773
    Abstract: The present invention relates to a colorimetric sensor chip includes a chemical reaction layer and a coloring reaction layer. The chemical reaction layer includes reaction zones reacting with a gas to be tested to produce a chemical change. The coloring reaction layer includes a coloring side and a reaction side in contact with the reaction zone which are opposite to each other. The coloring reaction layer further includes a coloring indicator to produce a coloring reaction corresponding to the chemical change of the reaction sides, thereby completing a light, thin and highly integrated gas sensor chip directly attaching or placing on an object to be sensed for real-time sensing.
    Type: Application
    Filed: March 20, 2020
    Publication date: September 24, 2020
    Inventors: Ching-Tung HSU, Chun-Wei SHIH, Kuang-Che LEE, Chia-Hung LI, Chien-Yao HUANG, Chun-Hsien TSAI, Ting-Chuan LEE, Chun-Jung TSAI
  • Publication number: 20200276596
    Abstract: A shower head includes a housing, and a jet faceplate mounted to the housing and including a first water jetting area composed of a plurality of subunits and a second water jetting area having a second jet hole therein. The subunits are arranged to present an arc-shaped distribution, each defining therein a plurality of first jet holes. The subunits are in a fan-shaped area of the jet faceplate so that the water line of the ejected water can be concentrated and fan-shaped, enhancing the effect of removing dirt.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Chun-Hung LI, Hui-Ling CHIU, Tun-Yao TSAI
  • Patent number: 10763409
    Abstract: Disclosed are an LED light source, an LED light source manufacturing method, and their direct display device. The LED light source includes a base, at least an LED chip, an anti-vulcanization structure, a light excitation structure, an encapsulation structure and a protection structure. The LED light source can overcome catalyst poison or vulcanization of the light-emitting material effectively to improve product yield and reliability of the LED light source. In the meantime, the LED light source has the feature of a better light emission performance.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: September 1, 2020
    Assignee: UNITY OPTO TECHNOLOGY CO., LTD.
    Inventors: Hung-Li Yeh, Wei-Chung Lin, Ko-Wei Lu
  • Patent number: 10763104
    Abstract: Methods of forming a differential layer, such as a Contact Etch Stop Layer (CESL), in a semiconductor device are described herein, along with structures formed by the methods. In an embodiment, a structure includes an active area on a substrate, a gate structure over the active area, a gate spacer along a sidewall of the gate structure, and a differential etch stop layer. The differential etch stop layer has a first portion along a sidewall of the gate spacer and has a second portion over an upper surface of the source/drain region. A first thickness of the first portion is in a direction perpendicular to the sidewall of the gate spacer, and a second thickness of the second portion is in a direction perpendicular to the upper surface of the source/drain region. The second thickness is greater than the first thickness.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ting Ko, Jr-Hung Li, Chi On Chui
  • Publication number: 20200274231
    Abstract: A mobile device includes a metal mechanism element, a dielectric substrate, a holder, a feeding radiation element, a ground plane, a shorting element, a circuit element, a first parasitic radiation element, a second parasitic radiation element, and an additional radiation element. The metal mechanism element has a slot. The ground plane and the shorting element are respectively coupled to the metal mechanism element. The circuit element is coupled between the shorting element and the ground plane. The first parasitic radiation element and the second parasitic radiation element are respectively coupled to the ground plane. The additional radiation element is adjacent to the feeding radiation element or is coupled to the feeding radiation element. An antenna structure is formed by the feeding radiation element, the circuit element, the first parasitic radiation element, the second parasitic radiation element, the additional radiation element, and the slot of the metal mechanism element.
    Type: Application
    Filed: October 31, 2019
    Publication date: August 27, 2020
    Inventors: Shih-Chiang WEI, Cheng-Da YANG, Kuan-Hung LI, Shu-Yun YEH
  • Patent number: 10756089
    Abstract: Present disclosure provides a hybrid semiconductor transistor structure, including a substrate, a first transistor on the substrate, a channel of the first transistor including a fin and having a first channel height, a second transistor adjacent to the first transistor, a channel of the second transistor including a nanowire, and a separation laterally spacing the fin from the nanowire. The first channel height is greater than the separation. Present disclosure also provides a method for manufacturing the hybrid semiconductor transistor structure.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang Chen
  • Publication number: 20200266271
    Abstract: Methods for forming semiconductor structures are provided. The method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate and patterning the first semiconductor layers and the second semiconductor layers to form a first fin structure. The method further includes forming a first trench in the first fin structure and forming a first source/drain structure in the first trench. The method further includes partially removing the first source/drain structure to form a second trench in the first source/drain structure and forming a first contact in the second trench.
    Type: Application
    Filed: May 7, 2020
    Publication date: August 20, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun LIN, Kuo-Hua PAN, Jhon-Jhy LIAW, Chao-Ching CHENG, Hung-Li CHIANG, Shih-Syuan HUANG, Tzu-Chiang CHEN, I-Sheng CHEN, Sai-Hooi YEONG
  • Patent number: 10749081
    Abstract: Disclosed are an LED light source, an LED light source manufacturing method, and their direct display device. The LED light source includes a base, at least an LED chip, an anti-vulcanization structure, a light excitation structure, an encapsulation structure and a protection structure. The LED light source can overcome catalyst poison or vulcanization of the light-emitting material effectively to improve product yield and reliability of the LED light source. In the meantime, the LED light source has the feature of a better light emission performance.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 18, 2020
    Assignee: UNITY OPTO TECHNOLOGY CO., LTD.
    Inventors: Hung-Li Yeh, Wei-Chung Lin, Ko-Wei Lu
  • Patent number: 10747080
    Abstract: An active device array substrate includes: a substrate, a switch device, an inter-layer dielectric layer, an insulation bump, a conductive layer, and a pixel electrode. The switch device is located on the substrate. The inter-layer dielectric layer is located on the switch device, and the inter-layer dielectric layer has at least one opening, where the opening does not cover at least one part of a drain electrode of the switch device. The insulation bump covers at least partially the opening. The conductive layer is located on a top surface and a side wall of the insulation bump, and is electrically connected to the drain electrode of the switch device through the opening. The pixel electrode is electrically connected to the conductive layer.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: August 18, 2020
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chang-Hung Li, Hsien-Hung Su, Ming-Hsien Lee
  • Patent number: 10727344
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chih Chieh Yeh, Cheng-Hsien Wu, Hung-Li Chiang, Jung-Piao Chiu, Tzu-Chiang Chen, Tsung-Lin Lee, Yu-Lin Yang, I-Sheng Chen
  • Patent number: 10727298
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Publication number: 20200235108
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a resistive random access memory cell, and a semiconductor element. The resistive random access memory cell is on the substrate. The resistive random access memory cell includes a first electrode having a U shape. The semiconductor element is adjoined with an outer sidewall of the first electrode.
    Type: Application
    Filed: April 7, 2020
    Publication date: July 23, 2020
    Inventor: Shin-Hung LI
  • Publication number: 20200215204
    Abstract: Disclosed is a (D331Y) PLA2G6 knockin mouse, which shows similar clinical symptoms to those of patients suffering from Parkinson's disease (PD), and begins to display early-onset cell death of dopaminergic neurons in its substantia nigra (SN), synucleinopathy, and tau pathology at the age of about 6 months, wherein the dopaminergic neurons exhibit mitochondrial structural abnormality and dysfunction. Treatment of the (D331Y) PLA2G6 knockin mouse with L-Dopa shows a good response. The (D331Y) PLA2G6 knockin mouse can be used as a platform for developing a medicament and method for treating PD.
    Type: Application
    Filed: July 31, 2019
    Publication date: July 9, 2020
    Inventors: Ching-Chi CHIU, Tu-Hsueh YEH, Hung-Li WANG
  • Publication number: 20200212191
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.
    Type: Application
    Filed: March 10, 2020
    Publication date: July 2, 2020
    Inventors: Yee-Chia YEO, Sung-Li WANG, Chi On CHUI, Jyh-Cherng SHEU, Hung-Li CHIANG, I-Sheng CHEN