Abstract: An apparatus includes a plurality of CPUs, a CPU scheduler, an idle predictor, and a CPU-idle framework. The CPUs are categorized into a first group and a second group, and a specific CPU is in the first group. When the specific CPU is idle, the CPU scheduler executes an idle task. The idle predictor determines whether the CPUs in the first group corresponding to the specific CPU are going to operate the sleep mode in response to the idle task so as to schedule a sleep schedule of the CPUs in the first group operating in the sleep mode. The CPU-idle framework commands the CPUs in the first group to operate in the sleep mode based on the sleep schedule.

Abstract: A carrier tray and a carrier tray assembly using the same are described. The carrier tray includes a carrying portion, a surrounding wall and at least one recessed structure. The carrying portion has a top surface and a bottom surface opposite to the top surface. The surrounding wall is disposed around the carrying portion. The recessed structure is recessed into the carrying portion. The recessed structure has an opening and a recessed space, and the recessed space is communicated with the outside through the opening. There is a first distance defined by the recessed space along a first direction, and there is a second distance defined by the opening along the first direction. The first distance is greater than the second distance.

Abstract: A packaging structure is used for carrying at least one carried object. The packaging structure includes a carrying unit and a covering member. The carrying unit includes a supporting plate, at least one first side plate connected to the edge of the supporting plate, and at least one combing member. The supporting plate has two opposite surfaces, and the first side plate is able to bend to one of the surfaces of the supporting plate, so that the carrying unit can be folded or unfolded. The first side plate is stacked on the supporting plate when the carrying unit is in the folded state, and the combing member keeps the first side plate stacked on the supporting plate. The covering member positions the carried object on the carrying unit. A delivering device is provided for clamping and positioning a plurality of the packaging structures in an upright manner.

Abstract: A carrier tray and a carrier tray assembly using the same are described. The carrier tray includes a carrying portion, a surrounding wall and at least one recessed structure. The carrying portion has a top surface and a bottom surface opposite to the top surface. The surrounding wall is disposed around the carrying portion. The recessed structure is recessed into the carrying portion. The recessed structure has an opening and a recessed space, and the recessed space is communicated with the outside through the opening. There is a first distance defined by the recessed space along a first direction, and there is a second distance defined by the opening along the first direction. The first distance is greater than the second distance.

Abstract: A packaging structure is used for carrying at least one carried object. The packaging structure comprises a carrying unit and a covering member. The carrying unit includes a supporting plate, at least one first side plate connected to the edge of the supporting plate, and at least one combing member. The supporting plate has two opposite surfaces, and the first side plate is able to bend to one of the surfaces of the supporting plate, so that the carrying unit is able to present as an unfolded state or a folded state. The first side plate is stacked on the supporting plate when the carrying unit is in the folded state, and the combing member keeps the first side plate stacked on the supporting plate. The covering member is used for positioning the carried object on the carrying unit. The invention also provides a delivering device for clamping and positioning a plurality of the aforementioned packaging structures in an upright manner.

Abstract: A multiprocessor system includes a first set of processors and a second set of processors. The first set of processors include a first set of standard cells and is configured to operate in a first frequency range. The second set of processors include a second set of standard cells and is configured to operate in a second frequency range. The first set of processors and the second set of processors have the same register-transfer level (RTL) description. Cells in the first set of standard cells have corresponding cells in the second set of standard cells with different characteristics. The first frequency range includes one or more frequencies higher than a maximum frequency in the second frequency range. The system also includes a clock generator that provides the same frequency to the first set of processors and the second set of processors.

Abstract: A method for performing processor resource allocation in an electronic device is provided, where the method may include the steps of: obtaining task-related information to determine whether a task of a plurality of tasks is a heavy task (e.g. the heavy task may correspond to heavier loading than others of the plurality of tasks), to selectively utilize a specific processor core within a plurality of processor cores to perform the task, and determining whether at least one scenario task exists within others of the plurality of tasks, to selectively determine according to application requirements a minimum processor core count and a minimum operating frequency for performing the at least one scenario task; and performing processor resource allocation according to a power table and system loading, to perform any remaining portion of the plurality of tasks. An apparatus for performing processor resource allocation according to the above method is provided.

Abstract: Energy efficiency is managed in a multi-cluster system. The system detects an event in which a current operating frequency of an active cluster enters or crosses any of one or more predetermined frequency spots of the active cluster, wherein the active cluster includes one or more first processor cores. When the event is detected, the system performs the following steps: (1) identifying a target cluster including one or more second processor cores, wherein the each first processor core in the first cluster and each second processor core in the second cluster have different energy efficiency characteristics; (2) activating at least one second processor core in the second cluster; (3) determining whether to migrate one or more interrupt requests from the first cluster to the second cluster; and (4) determining whether to deactivate at least one first processor core of the active cluster based on a performance and power requirement.

Abstract: A multi-cluster system having processor cores of different energy efficiency characteristics is configured to operate with high efficiency such that performance and power requirements can be satisfied. The system includes multiple processor cores in a hierarchy of groups. The hierarchy of groups includes: multiple level-1 groups, each level-1 group including one or more of processor cores having identical energy efficiency characteristics, and each level-1 group configured to be assigned tasks by a level-1 scheduler; one or more level-2 groups, each level-2 group including respective level-1 groups, the processor cores in different level-1 groups of the same level-2 group having different energy efficiency characteristics, and each level-2 group configured to be assigned tasks by a respective level-2 scheduler; and a level-3 group including the one or more level-2 groups and configured to be assigned tasks by a level-3 scheduler.

Abstract: A multi-core processor system and method are provided. The multi-core processor system includes a plurality of processor cores and a task scheduler. The processor cores perform a plurality of tasks, wherein each of the tasks is in a respective one of a plurality of scheduling classes. The task scheduler obtains first task assignment information about tasks which are in a first scheduling class from the scheduling classes and assigned to the processor cores, obtains second task assignment information about tasks in one or more other scheduling classes and assigned to the processor cores, and refers to the first task assignment information and the second task assignment information to assign a runnable task in the first scheduling class to one of the processor cores. Prior to the assigning the runnable task, the runnable task has been assigned to one of the processor cores.

Abstract: A task scheduling method is applied to a heterogeneous multi-core processor system. The heterogeneous multi-core processor system has at least one first processor core and at least one second processor core. The task scheduling method includes: referring to task priorities of tasks of the heterogeneous processor cores to identify at least one first task of the tasks that belongs to a first priority task group, wherein each first task belonging to the first priority task group has a task priority not lower than task priorities of other tasks not belonging to the first priority task group; and dispatching at least one of the at least one first task to at least one run queue of at least one of the at least one first processor core.

Abstract: A multi-core processor system and a method for assigning tasks are provided. The multi-core processor system includes a plurality of processor cores, configured to perform a plurality of tasks, and each of the tasks is in a respective one of a plurality of scheduling classes. The multi-core processor system further includes a task scheduler, configured to obtain first task assignment information about tasks in a first scheduling class assigned to the processor cores, obtain second task assignment information about tasks in one or more other scheduling classes assigned to the processor cores, and refer to the first task assignment information and the second task assignment information to assign a runnable task in the first scheduling class to one of the processor cores.

Abstract: A multiprocessor system includes a first set of processors and a second set of processors. The first set of processors include a first set of standard cells and is configured to operate in a first frequency range. The second set of processors include a second set of standard cells and is configured to operate in a second frequency range. The first set of processors and the second set of processors have the same register-transfer level (RTL) description. Cells in the first set of standard cells have corresponding cells in the second set of standard cells with different characteristics. The first frequency range includes one or more frequencies higher than a maximum frequency in the second frequency range. The system also includes a clock generator that provides the same frequency to the first set of processors and the second set of processors.

Abstract: A CPU control method for controlling a first CPU and a second CPU The method comprises: (a) applying the first CPU to execute a first group of codes comprising at least one code if the first CPU is operating to perform a first function; and (c) applying the second CPU to execute a second group of codes comprising at least one code if the second CPU is operating to perform the first function. The first group of codes is optimized for the first CPU, the second group of codes is optimized for the second CPU and the first group of codes comprises at least one code different from the code for the second group of codes.

Abstract: A switch interconnect is dynamically controlled at runtime to connect power sources to processing units in a multiprocessor system. Each power source is shareable by the processing units and each processing unit has a required voltage for processing a workload. When a system condition is detected at runtime, the switch interconnect is controlled to change a connection between at least one processing unit and a shared power source to maximize power efficiency. The shared power source is one of the power sources that supports multiple processing units having different required voltages.

Abstract: A method for performing processor resource allocation in an electronic device is provided, where the method may include the steps of: obtaining task-related information to determine whether a task of a plurality of tasks is a heavy task (e.g. the heavy task may correspond to heavier loading than others of the plurality of tasks), to selectively utilize a specific processor core within a plurality of processor cores to perform the task, and determining whether at least one scenario task exists within others of the plurality of tasks, to selectively determine according to application requirements a minimum processor core count and a minimum operating frequency for performing the at least one scenario task; and performing processor resource allocation according to a power table and system loading, to perform any remaining portion of the plurality of tasks. An apparatus for performing processor resource allocation according to the above method is provided.

Abstract: A computing system with multiple processor cores manages power and performance by dynamic frequency scaling. The system detects a condition when a total number of active processor cores within one or more clusters is less than a predetermined number, and an operating frequency of the active processor cores has risen to a specified highest frequency. The system also obtains ambient temperature measurement of the one or more clusters. Upon detecting the condition, the system increases the operating frequency above the specified highest frequency based on the ambient temperature measurement while maintaining a same level of supply voltage to the active processor cores.

Abstract: A computing system supports a clearance mode for its processor cores. The computing system can transition a target processor core from an active mode into a clearance mode according to a system policy. The system policy determines the number of processor cores to be in the active mode. The transitioning into the clearance mode includes the operations of migrating work from the target processor core to one or more other processor cores in the active mode in the computing system; and removing the target processor core from a scheduling configuration of the computing system to prevent task assignment to the target processor core. When the target processor core is in the clearance mode, the target processor core is maintained in an online idle state in which the target processor core performs no work.

Abstract: A mode switching handling method includes: when an operating system mode is switched from a first mode to a second mode, saving only a portion of register data that are stored in registers into a storage device, wherein an M-bit register length is used in the first mode, an N-bit register length is used in the second mode, and M and N are different integers.

Abstract: A CPU control method for controlling a first CPU and a second CPU The method comprises: (a) applying the first CPU to execute a first group of codes comprising at least one code if the first CPU is operating to perform a first function; and (c) applying the second CPU to execute a second group of codes comprising at least one code if the second CPU is operating to perform the first function. The first group of codes is optimized for the first CPU, the second group of codes is optimized for the second CPU and the first group of codes comprises at least one code different from the code for the second group of codes.