Patents by Inventor Hung-Lin Shih
Hung-Lin Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8536653Abstract: A metal oxide semiconductor transistor includes a substrate including a first well, a second well, and an insulation between the first well and the second well, a first gate structure disposed on the first well, a second gate structure disposed on the second well, four first dopant regions disposed in the substrate at two sides of the first gate structure, and in the substrate at two sides of the second gate structure respectively, two second dopant regions disposed in the substrate at two sides of the first gate structure respectively, two first epitaxial layers disposed in the substrate at two sides of the first gate structure respectively and two first source/drain regions disposed in the substrate at two sides of the first gate structure respectively, wherein each of the first source/drain regions overlaps with one of the first epitaxial layers and one of the second dopant regions simultaneously.Type: GrantFiled: October 14, 2010Date of Patent: September 17, 2013Assignee: United Microelectronics Corp.Inventors: Hung-Lin Shih, Tsan-Chi Chu
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Patent number: 8409945Abstract: A method of fabricating a non-volatile memory cell is disclosed. The method includes the steps of: forming two separate charge trapping structures on a semiconductor substrate; forming first spacers on sidewalls of the two charge trapping structures; forming a gate dielectric layer on the substrate; forming a gate on the two charge trapping structures and the gate dielectric layer between the two charge trapping structures; and forming two doped regions in the substrate beside the gate.Type: GrantFiled: January 5, 2011Date of Patent: April 2, 2013Assignee: United Microelectronics Corp.Inventors: Hung-Lin Shih, Tsan-Chi Chu
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Patent number: 8389358Abstract: A non-volatile memory structure includes a substrate; a poly gate structure formed on the substrate; a contact etching stop layer formed over the poly gate structure and including at least a silicon nitride layer and a first silicon oxide layer overlying the silicon nitride layer; and an inter-layer dielectric layer formed on the first silicon oxide layer. The first silicon oxide layer has a density higher than that of the inter-layer dielectric layer.Type: GrantFiled: July 22, 2011Date of Patent: March 5, 2013Assignee: United Microelectronics Corp.Inventors: Hung-Lin Shih, Chih-Ta Chen
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Patent number: 8362535Abstract: A non-volatile memory cell includes a semiconductor substrate with isolation structures formed therein and thereby transistor region and capacitor region are defined therein. A conductor is disposed over the isolation structures, the transistor region and a first-type doped well disposed in the capacitor region. The conductor includes a capacitor portion disposed over the first-type doped well, a transistor portion disposed over the transistor region, a first edge disposed over the isolation structure at a side of the transistor region, and an opposite second edge disposed over the first-type doped well. Two first ion doped wells are disposed in the transistor region and respectively at two sides of the transistor portion, and constitutes a transistor with the transistor portion. A second ion doped region is disposed in the capacitor region excluding the conductor and constitutes a capacitor with the capacitor portion.Type: GrantFiled: September 29, 2009Date of Patent: January 29, 2013Assignee: United Microelectronics Corp.Inventors: Hung-Lin Shih, Jr-Bin Chen, Pei-Ching Yin, Hui-Fang Tsai
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Publication number: 20130020625Abstract: A non-volatile memory structure includes a substrate; a poly gate structure formed on the substrate; a contact etching stop layer formed over the poly gate structure and including at least a silicon nitride layer and a first silicon oxide layer overlying the silicon nitride layer; and an inter-layer dielectric layer formed on the first silicon oxide layer. The first silicon oxide layer has a density higher than that of the inter-layer dielectric layer.Type: ApplicationFiled: July 22, 2011Publication date: January 24, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hung-Lin SHIH, Chih-Ta CHEN
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Patent number: 8320960Abstract: A docking station includes a casing, a socket and a plurality of peripheral interface devices. The casing includes a base and a cover, wherein the cover is pivotingly disposed on the base, openably and coverably, to form an appearance of a notebook computer. The socket is formed in a surface of the base for receiving a mobile communication device, and a high speed transmission interface is formed in a bottom of the socket. The plurality of peripheral interface devices is disposed on the casing and electrically connected with the high speed transmission interface. When the mobile communication device is placed in the socket, the mobile communication device is electrically connected with the high speed transmission interface and transmits signals with the plurality of peripheral interface devices. Basing on the structure, the present invention can ensure that mobile communication devices are convenient for operation.Type: GrantFiled: July 21, 2009Date of Patent: November 27, 2012Assignee: Azurewave Technologies, Inc.Inventor: Hung-Lin Shih
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Patent number: 8232591Abstract: An illuminating efficiency-increasable and light-erasable memory including a substrate, a memory device, many dielectric layers, and many cap layers is provided. The substrate includes a memory region. The memory device includes a select gate and a floating gate, and the select gate and the floating gate are disposed adjacently on the substrate in the memory region. The dielectric layers are disposed on the substrate and cover the memory device. The dielectric layers have an opening located above the floating gate. Each of the cap layers is disposed on each of the dielectric layers, respectively.Type: GrantFiled: April 28, 2009Date of Patent: July 31, 2012Assignee: United Microelectronics Corp.Inventors: Hung-Lin Shih, Wen-Ching Tsai, Yu-Hua Huang
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Patent number: 8022503Abstract: An anti-fuse structure and a method of fabricating the same are described. The anti-fuse structure is disposed over a substrate having at least one device and a copper layer therein. The anti-fuse structure includes a bottom conductive layer, an insulating layer and a top conductive layer. The bottom conductive layer is disposed over and electrically connected with the copper layer. The insulating layer is conformally disposed over the bottom conductive layer covering a corner or a downward turning portion of the bottom conductive layer to form a turning portion of the insulating layer. The top conductive layer is conformally disposed over the insulting layer covering the turning portion of the insulating layer.Type: GrantFiled: June 3, 2008Date of Patent: September 20, 2011Assignee: United Microelectronics Corp.Inventors: Hung-Lin Shih, Wen-Shiang Liao, Tsan-Chi Chu
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Patent number: 7998821Abstract: A method of manufacturing a CMOS is disclosed. A substrate has a first gate and a second gate. A dielectric layer and a patterned photo-resist layer are formed sequentially on the substrate. After an etching process, the dielectric layer without the photo-resist layer forms a spacer around the first gate, and the dielectric layer with the photo-resist layer forms a block layer on the second gate. The recesses are formed in the substrate of two lateral sides of the first gate. The epitaxial silicon layers are formed in the recesses.Type: GrantFiled: October 5, 2006Date of Patent: August 16, 2011Assignee: United Microelectronics Corp.Inventors: Hung-Lin Shih, Tsan-Chi Chu
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Publication number: 20110097866Abstract: A method of fabricating a non-volatile memory cell is disclosed. The method includes the steps of: forming two separate charge trapping structures on a semiconductor substrate; forming first spacers on sidewalls of the two charge trapping structures; forming a gate dielectric layer on the substrate; forming a gate on the two charge trapping structures and the gate dielectric layer between the two charge trapping structures; and forming two doped regions in the substrate besdie the gate.Type: ApplicationFiled: January 5, 2011Publication date: April 28, 2011Inventors: Hung-Lin Shih, Tsan-Chi Chu
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Publication number: 20110073924Abstract: A non-volatile memory cell includes a semiconductor substrate with isolation structures formed therein and thereby transistor region and capacitor region are defined therein. A conductor is disposed over the isolation structures, the transistor region and a first-type doped well disposed in the capacitor region. The conductor includes a capacitor portion disposed over the first-type doped well, a transistor portion disposed over the transistor region, a first edge disposed over the isolation structure at a side of the transistor region, and an opposite second edge disposed over the first-type doped well. Two first ion doped wells are disposed in the transistor region and respectively at two sides of the transistor portion, and constitutes a transistor with the transistor portion. A second ion doped region is disposed in the capacitor region excluding the conductor and constitutes a capacitor with the capacitor portion.Type: ApplicationFiled: September 29, 2009Publication date: March 31, 2011Inventors: Hung-Lin SHIH, Bin Chen, JR., Pei-Ching Yin, Hui-Fang Tsai
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Patent number: 7902587Abstract: A non-volatile memory cell is described, including a semiconductor substrate, two separate charge trapping structures on the substrate, first spacers at least on the opposite sidewalls of the two charge trapping structures, a gate dielectric layer on the substrate between the two charge trapping structures, a gate on the two charge trapping structures and the gate dielectric layer, and two doped regions in the substrate beside the gate.Type: GrantFiled: April 17, 2008Date of Patent: March 8, 2011Assignee: United Microelectronics Corp.Inventors: Hung-Lin Shih, Tsan-Chi Chu
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Publication number: 20110031555Abstract: A metal oxide semiconductor transistor includes a substrate including a first well, a second well, and an insulation between the first well and the second well, a first gate structure disposed on the first well, a second gate structure disposed on the second well, four first dopant regions disposed in the substrate at two sides of the first gate structure, and in the substrate at two sides of the second gate structure respectively, two second dopant regions disposed in the substrate at two sides of the first gate structure respectively, two first epitaxial layers disposed in the substrate at two sides of the first gate structure respectively and two first source/drain regions disposed in the substrate at two sides of the first gate structure respectively, wherein each of the first source/drain regions overlaps with one of the first epitaxial layers and one of the second dopant regions simultaneously.Type: ApplicationFiled: October 14, 2010Publication date: February 10, 2011Inventors: Hung-Lin Shih, Tsan-Chi Chu
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Publication number: 20110021247Abstract: A docking station includes a casing, a socket and a plurality of peripheral interface devices. The casing includes a base and a cover, wherein the cover is pivotingly disposed on the base, openably and coverably, to form an appearance of a notebook computer. The socket is formed in a surface of the base for receiving a mobile communication device, and a high speed transmission interface is formed in a bottom of the socket. The plurality of peripheral interface devices is disposed on the casing and electrically connected with the high speed transmission interface. When the mobile communication device is placed in the socket, the mobile communication device is electrically connected with the high speed transmission interface and transmits signals with the plurality of peripheral interface devices. Basing on the structure, the present invention can ensure that mobile communication devices are convenient for operation.Type: ApplicationFiled: July 21, 2009Publication date: January 27, 2011Inventor: HUNG-LIN SHIH
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Patent number: 7732886Abstract: A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.Type: GrantFiled: July 15, 2008Date of Patent: June 8, 2010Assignee: United Microelectronics Corp.Inventors: Hung-Lin Shih, Tsan-Chi Chu, Wen-Shiang Liao, Wen-Ching Tsai
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Publication number: 20100012974Abstract: A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.Type: ApplicationFiled: July 15, 2008Publication date: January 21, 2010Inventors: Hung-Lin Shih, Tsan-Chi Chu, Wen-Shiang Liao, Wen-Ching Tsai
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Patent number: 7639536Abstract: A storage unit of a single-conductor non-volatile memory cell is described, which includes an isolation layer in a substrate, a storage transistor and an erasing transistor. The storage transistor includes a first well of a first conductivity type in the substrate beside the isolation layer, a floating gate crossing over the isolation layer and including a first segment over the first well, and two source/drain regions of a second conductivity type in the first well beside the first segment of the floating gate. The erasing transistor includes a second well of the first conductivity type located in the substrate and separated from the first well by the isolation layer, a second segment of the floating gate over the second well, and a well pickup region of the first conductivity type in the second well beside the second segment of the floating gate.Type: GrantFiled: March 7, 2008Date of Patent: December 29, 2009Assignee: United Microelectronics Corp.Inventors: Hung-Lin Shih, Wen-Ching Tsai, Yu-Hua Huang
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Publication number: 20090294903Abstract: An anti-fuse structure and a method of fabricating the same are described. The anti-fuse structure is disposed over a substrate having at least one device and a copper layer therein. The anti-fuse structure includes a bottom conductive layer, an insulating layer and a top conductive layer. The bottom conductive layer is disposed over and electrically connected with the copper layer. The insulating layer is conformally disposed over the bottom conductive layer covering a corner or a downward turning portion of the bottom conductive layer to form a turning portion of the insulating layer. The top conductive layer is conformally disposed over the insulting layer covering the turning portion of the insulating layer.Type: ApplicationFiled: June 3, 2008Publication date: December 3, 2009Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hung-Lin Shih, Wen-Shiang Liao, Tsan-Chi Chu
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Publication number: 20090261401Abstract: A non-volatile memory cell is described, including a semiconductor substrate, two separate charge trapping structures on the substrate, first spacers at least on the opposite sidewalls of the two charge trapping structures, a gate dielectric layer on the substrate between the two charge trapping structures, a gate on the two charge trapping structures and the gate dielectirc layer, and two doped regions in the substrate beside the gate.Type: ApplicationFiled: April 17, 2008Publication date: October 22, 2009Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hung-Lin Shih, Tsan-Chi Chu
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Publication number: 20090225601Abstract: A storage unit of a single-conductor non-volatile memory cell is described, which includes an isolation layer in a substrate, a storage transistor and an erasing transistor. The storage transistor includes a first well of a first conductivity type in the substrate beside the isolation layer, a floating gate crossing over the isolation layer and including a first segment over the first well, and two source/drain regions of a second conductivity type in the first well beside the first segment of the floating gate. The erasing transistor includes a second well of the first conductivity type located in the substrate and separated from the first well by the isolation layer, a second segment of the floating gate over the second well, and a well pickup region of the first conductivity type in the second well beside the second segment of the floating gate.Type: ApplicationFiled: March 7, 2008Publication date: September 10, 2009Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hung-Lin Shih, Wen-Ching Tsai, Yu-Hua Huang