Abstract: A latch calibration system includes a latch, a clock circuit and a calibration circuit. Latch latches logic data from a data node in an internal node. Latch includes two transistors respectively coupled between data node and internal node. Clock circuit generates first and second clock control signals. Calibration circuit is coupled to clock circuit and latch, and includes two bootstrap circuits coupled to clock circuit respectively. First bootstrap circuit generates a third clock control signal according to first clock control signal, which is output to a gate of first transistor. a high level of third clock control signal is greater than that of first clock control signal. Second bootstrap circuit generates a fourth clock control signal according to the second clock control signal, which is output to a gate of second transistor. A low level of fourth clock control signal is less than that of second clock control signal.

Abstract: A control device includes multi-stage control circuits. An i-th stage control circuit includes an input signal generator and an acknowledge signal generator. The input signal generator generates an i+1-th stage input signal according to a first inverted output signal and an i+1-th stage acknowledge signal. The acknowledge signal generator generates an i-th stage acknowledge signal according to an i-th stage delayed input signal and a second inverted output signal, wherein i is an integer larger than 1. Phases of the first inverted output signal and the second inverted output signal are opposite to a phase of an i-th stage output signal generated by an i-th stage pulse signal generator.