Patents by Inventor Hung LO
Hung LO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250100870Abstract: A controller for controlling a sound producing device includes a vent controller and an audio amplifier. The vent controller is configured to output a first driving voltage and a second driving voltage to the sound producing device, to control the sound producing device to form a vent. The audio amplifier is configured to output a first audio signal to the sound producing device, to produce a sound. The sound producing device comprises a flap pair, and the flap pair comprises a first flap and a second flap. The vent controller outputs the first driving voltage and actuates the first flap to generate a first displacement, the vent controller outputs the second driving voltage and actuates the second flap to generate a second displacement, and the vent is formed because of a difference between the first displacement and the second displacement.Type: ApplicationFiled: December 11, 2024Publication date: March 27, 2025Applicant: xMEMS Labs, Inc.Inventors: Ming-Hung Chang, Chiung C. Lo
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Patent number: 12261092Abstract: A semiconductor package includes a semiconductor device, an encapsulating material, a redistribution structure, and an adhesive residue. The encapsulating material encapsulates a first part of a side surface of the semiconductor device. The redistribution structure is disposed over the semiconductor device and a first side of the encapsulating material. The adhesive residue is disposed over a second side of the encapsulating material opposite to the first side and surrounding the semiconductor device, wherein the adhesive residue encapsulates a second part of the side surface of the semiconductor device.Type: GrantFiled: August 30, 2021Date of Patent: March 25, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Sung Huang, Ming-Hung Tseng, Yen-Liang Lin, Ban-Li Wu, Hsiu-Jen Lin, Teng-Yuan Lo, Hao-Yi Tsai
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Publication number: 20250072814Abstract: A transcutaneous electrical stimulation system is provided that can include a number of features. In one implementation, the system can include a plurality of electrodes configured to be in contact with a skin surface of a patient. The system can further include a flexible hub electrically connected to the electrodes and configured to be in contact with the patient. A bend sensor can be disposed in the hub and configured to measure a curvature of the hub. The system can include a signal processing device electrically coupled to the plurality of electrodes and the bend sensor, the signal processing device being configured to change stimulation settings of the plurality of electrodes based on the curvature of the hub. In some implementations, the system can include a multi-channel stimulator. Methods of use are also provided.Type: ApplicationFiled: November 19, 2024Publication date: March 6, 2025Inventors: Yi-Kai LO, Rachel YUNG, Po-Min WANG, Alexander Barnes BALDWIN, Chia-Hung NI
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Publication number: 20250072976Abstract: The augmented reality system includes a needle, a camera, an ultrasound generator, a memory, and a processor. The needle includes a location code, a first marking area, and a second marking area. The processor is used to perform following steps: capturing the location code, the first marking area, and the second marking area of the needle to perform positioning or a marking pose estimation by the camera; obtaining a feature points number according to the first marking area and the second marking area; obtaining a range prediction interval of the ultrasound field of view according to the feature points number of the needle; increasing or decreasing the range prediction interval according to the feature points number and a feature points number threshold; and when it is determined that the feature points number is greater than the feature points number threshold, the range prediction interval is reduced.Type: ApplicationFiled: March 26, 2024Publication date: March 6, 2025Inventors: Min-Hung LO, Hao-Li LIU
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Publication number: 20250081730Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.Type: ApplicationFiled: June 26, 2024Publication date: March 6, 2025Inventors: Andrew Lin, Alper Ozgurluk, Chao Liang Chien, Cheuk Chi Lo, Chia-Yu Chen, Chien-Chung Wang, Chih Pang Chang, Chih-Hung Yu, Chih-Wei Chang, Chin Wei Hsu, ChinWei Hu, Chun-Kai Tzeng, Chun-Ming Tang, Chun-Yao Huang, Hung-Che Ting, Jung Yen Huang, Lungpao Hsin, Shih Chang Chang, Tien-Pei Chou, Wen Sheng Lo, Yu-Wen Liu, Yung Da Lai
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Patent number: 12242321Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.Type: GrantFiled: April 27, 2023Date of Patent: March 4, 2025Assignee: ASUSTEK COMPUTER INC.Inventors: Wen Che Chung, Hui Chuan Lo, Hao-Hsuan Lin, Chun Tsao, Jun-Fu Chen, Ming-Hung Yao, Jia-Wei Zhang, Kuan-Lun Chen, Ting-Chao Lin, Cheng-Yen Lin, Chunyen Lai
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Publication number: 20250044322Abstract: The present invention provides a quick coupling probe card, utilized to test circuit board. The quick coupling probe card comprises a base, a coaxial connector, mechanical connector, and probe holding part, wherein the base has a first surface and a second surface corresponding to the first surface, the coaxial connector arranged on the base has one end above the first surface, and is coupled to the test machine for transmitting the high frequency signal, the mechanical connector is arranged on the first surface for coupling to the test machine, and is closer to a center of the base than the coaxial connector, and the probe holding part, arranged on the second surface and utilized to couple to the coaxial connector, has one end connected to a high frequency probe corresponding to one specific kind of the different kinds of pitches.Type: ApplicationFiled: May 23, 2024Publication date: February 6, 2025Inventors: Ya-Hung Lo, Chien-Hsun Chen, Chia-Nan Chou, Shou-Jen Tsai, Fuh-Chyun Tang
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Publication number: 20250046734Abstract: A package includes a first package component; a second package component bonded to the first package component by a first plurality of solder connectors; and a first plurality of spacer connectors extending from the first package component to the second package component. A diameter of a spacer connector the first plurality of spacer connectors is larger than a height of a solder connector of the first plurality of solder connectors, and the first plurality of spacer connectors comprises a different material than the first plurality of solder connectors.Type: ApplicationFiled: October 19, 2023Publication date: February 6, 2025Inventors: Wei-Hung Lin, Chi-Chun Hsieh, Ming-Hua Lo, Chung-Chih Chen, Hsin-Hsien Wu
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Patent number: 12218180Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a first metal nitride structure, a second metal nitride structure spaced from the first metal nitride structure, and a metal structure disposed between the first metal nitride structure and the second metal nitride structure. A first dielectric structure is disposed over the substrate and the resistor.Type: GrantFiled: August 7, 2023Date of Patent: February 4, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Hsien Lo, Che-Hung Liu, Tzu-Chung Tsai
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Patent number: 12210096Abstract: A radar system includes an ultrasonic radar unit and a warning device. The ultrasonic radar unit is configured to be detachably mounted on a vehicle, and is configured to output a pairing signal when a pairing function is activated and output a warning signal upon detecting an object that is within a range. The warning device is configured to be electrically connected to the ultrasonic radar unit and to be mounted inside the vehicle. The warning device is configured to wirelessly communicate with the ultrasonic radar unit to receive the warning signal and the pairing signal; when receiving the pairing signal, couple the ultrasonic radar unit to one of a plurality of warning areas that is on the warning device according to the pairing signal; control one of the warning areas that is coupled to the ultrasonic radar unit to output a visual warning upon receiving the warning signal.Type: GrantFiled: July 3, 2023Date of Patent: January 28, 2025Assignee: Vision Automobile Electronics Industrial Co., Ltd.Inventors: Tien-Bou Wan, Chung-Hsiao Lo, Chien-Liang Pan, An-Hun Cheng, Chia-Hung Wu
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Patent number: 12194667Abstract: The present invention discloses a high temperature resistant outer layer covering aerogel composite material with low dielectric, high heat insulation and high fireproof characteristics and preparation method thereof. The method comprises steps of: (1) mixing hydrolysis, (2) condensation and dispersion, (3) structure molding, (4) atmospheric pressure drying, (5) outer layer covering, (6) curing molding and (7) surface treatment. In this technology, a trace amount of water-dispersible high temperature resistant glue is added to the aerogel sol in the step of condensation and dispersion, which is injected into the fiber-containing preformed structure, and dried at high temperature and atmospheric to prepare aerogel preformed materials. And then, the aerogel preformed materials are wrapped by a high temperature resistant material and cured to prepare the aerogel composite material with low dielectric, high heat insulation and high fireproof properties.Type: GrantFiled: April 25, 2023Date of Patent: January 14, 2025Assignee: Taiwan Aerogel Technology Material Co., Ltd.Inventors: Jean-Hong Chen, Cheng-Shu Chiang, Ya-Chi Ko, Chi-Hung Lo, Wen-Yen Hsu
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Publication number: 20250011414Abstract: The present invention relates to compositions and methods utilizing anti-TNF antibodies having a heavy chain (HC) comprising SEQ ID NO:36 and a light chain (LC) comprising SEQ ID NO:37 for use in the safe and effective treatment of active Psoriatic Arthritis (PsA).Type: ApplicationFiled: September 19, 2024Publication date: January 9, 2025Inventors: Diane D. Harrison, Elizabeth C. Hsia, Lee-Lian Kim, Kim Hung Lo
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Patent number: 12193205Abstract: A static random access memory device is provided and includes a first gate of a first pass-gate transistor extending to cross a first number of fins in a first threshold voltage region of a substrate and a second gate of a second pass-gate transistor extending to cross a second number of fins in a second threshold voltage region of a substrate. A boundary of the first threshold voltage region between the first and second gates is arranged closer to one, which crosses a smaller number of fins, of the first and second gates.Type: GrantFiled: May 5, 2023Date of Patent: January 7, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Hung Lo, Feng-Ming Chang, Ying-Hsiu Kuo
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Publication number: 20240402740Abstract: Power supply circuits in which a supplemental current driver is utilized to boost the current provided by a voltage regulator. The supplementing driver detects operating conditions for providing the supplementary current, and may be trained to provide particular amounts of current in response to particular operation conditions of a circuit load.Type: ApplicationFiled: June 1, 2023Publication date: December 5, 2024Applicant: NVIDIA Corp.Inventors: Zhonghua Li, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir, Jaewon Lee, Jiwang Lee, CHUNJEN SU
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Publication number: 20240393386Abstract: A method for adjusting position of probing base comprises steps of providing a probing machine comprising a probing holder, a first probing base having a first probing needle comprising a plurality of first probing bodies wherein two adjacent tips of the first probing bodies h a first pitch, and a second probing base having a second probe comprising a plurality of second probing bodies in which two adjacent tips of the second probing bodies has a second pitch, thereafter, grabbing the first probing base and connecting the first probing base to the probing holder, acquiring first image with respect to the plurality of first probing bodies through visual identification module, and finally, adjusting roll angle of probing tips of the plurality of first needle bodies according to the first image. Alternatively, the present invention further provides a probing machine using the method for testing DUTs having different pitches.Type: ApplicationFiled: May 23, 2024Publication date: November 28, 2024Inventors: YA-HUNG LO, CHIEN-HSUN CHEN, SHOU-JEN TSAI, FUH-CHYUN TANG
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Publication number: 20240373615Abstract: A static random access memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.Type: ApplicationFiled: July 15, 2024Publication date: November 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shau-Wei LU, Hao CHANG, Kun-Hsi LI, Kuo-Hung LO, Kang-Yu HSU, Yao-Chung HU
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Publication number: 20240359379Abstract: The present invention discloses a high temperature resistant outer layer covering aerogel composite material with low dielectric, high heat insulation and high fireproof characteristics and preparation method thereof. The method comprises steps of: (1) mixing hydrolysis, (2) condensation and dispersion, (3) structure molding, (4) atmospheric pressure drying, (5) outer layer covering, (6) curing molding and (7) surface treatment. In this technology, a trace amount of water-dispersible high temperature resistant glue is added to the aerogel sol in the step of condensation and dispersion, which is injected into the fiber-containing preformed structure, and dried at high temperature and atmospheric to prepare aerogel preformed materials. And then, the aerogel preformed materials are wrapped by a high temperature resistant material and cured to prepare the aerogel composite material with low dielectric, high heat insulation and high fireproof properties.Type: ApplicationFiled: April 25, 2023Publication date: October 31, 2024Inventors: JEAN-HONG CHEN, CHENG-SHU CHIANG, YA-CHI KO, CHI-HUNG LO, WEN-YEN HSU
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Publication number: 20240355986Abstract: A micro light-emitting diode package structure and a forming method thereof are provided. The micro light-emitting diode package structure includes micro light-emitting diode dies, a light-transmitting layer, a first insulating layer, redistribution layers, and conductive elements. The micro light-emitting diode dies are disposed side by side and each includes an electrode surface, a light-emitting surface, and side surfaces. The electrode surface and the light-emitting surface are opposite to each other, and the side surfaces are between them. The light-transmitting layer covers the light-emitting surface and the side surfaces. The first insulating layer is under the micro light-emitting diode dies and in direct contact with the electrode surface. The redistribution layers are disposed under the first insulating layer and pass through the first insulating layer to electrically connect the electrode surface.Type: ApplicationFiled: April 11, 2024Publication date: October 24, 2024Inventors: Shiou-Yi KUO, Guo-Yi SHIU, Chin-Hung LO, Chih-Hao LIN, Cheng-Hsien LI, Wei-Yuan MA
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Patent number: 12122824Abstract: The present invention relates to compositions and methods utilizing anti-TNF antibodies having a heavy chain (HC) comprising SEQ ID NO:36 and a light chain (LC) comprising SEQ ID NO:37 for use in the safe and effective treatment of active Psoriatic Arthritis (PsA).Type: GrantFiled: May 14, 2021Date of Patent: October 22, 2024Assignee: Janssen Biotech, Inc.Inventors: Diane D. Harrison, Elizabeth C. Hsia, Lee-Lian Kim, Kim Hung Lo
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Publication number: 20240349475Abstract: An IC structure includes a first gate strip and a first active region under the first gate strip and forming a first transistor with the first gate strip. From a top view, the first active region has opposite short sides and opposite long sides connecting the short sides and longer than the short sides. First one of the long sides has a first stepped top-view profile. Second one of the long sides has a second stepped top-view profile. The first stepped top-view profile has more step rises than the second stepped top-view profile.Type: ApplicationFiled: June 26, 2024Publication date: October 17, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Gulbagh SINGH, Shun-Chi TSAI, Chih-Ming LEE, Chi-Yen LIN, Kuo-Hung LO