Abstract: An image processing device includes a CSA accumulator, a first register, a CPA adder and a central processing unit. The CSA accumulator includes a first input for receiving a processing signal and a second input for receiving a previous result of the CSA accumulator. The first register includes an input coupled to the CSA accumulator and an output coupled to the second input end of the CSA accumulator. The CPA adder is coupled to the first register. The CPA adder is used for processing an addition operation on all carries outputted from the first register. The central processing unit includes an input coupled to the CPA adder and an output end for outputting an output signal comprising processed image measurement data.

Abstract: An image processing device includes a CSA accumulator, a first register, a CPA adder and a central processing unit. The CSA accumulator includes a first input for receiving a processing signal and a second input for receiving a previous result of the CSA accumulator. The first register includes an input coupled to the CSA accumulator and an output coupled to the second input end of the CSA accumulator. The CPA adder is coupled to the first register. The CPA adder is used for processing an addition operation on all carries outputted from the first register. The central processing unit includes an input coupled to the CPA adder and an output end for outputting an output signal comprising processed image measurement data.

Abstract: A data transformation device including a pre-processing unit, a calculating unit and a post-processing unit is disclosed. The pre-processing unit performs a first pre-process with received image data to generate pre-processed image data, and performs a second pre-process with received result data to generate pre-processed result data. The calculating unit generates first calculated data and second calculated data according to the pre-processed image data and the pre-processed result data, by both a first calculating component and a second calculating component respectively. The post-processing unit performs a first post-process to generate the result data according to the first calculating data, and performs a second post-process to generate the image data according to the second calculating data.

Abstract: A data transformation method capable of saving numeral operations, the data transformation method includes encoding a plurality of digital data to generate a plurality of sets of byte data according to an encoding mode, determining a plurality of repetition patterns of the plurality of sets of byte data, processing shift operations on the plurality of sets of byte data to generate a plurality of sets of shifted byte data according to positions of the plurality of repetition patterns located in the plurality of sets of byte data, processing addition operations on the plurality of sets of shifted byte data.

Abstract: A sigma-delta circuit with time sharing architecture includes a coefficient generation element, a sigma-delta processing element, and a storage element. The coefficient generation element is used for generating coefficients for sigma-delta operations. The sigma-delta processing element is used for executing sigma-delta operations according to the coefficients generated by the coefficient generation element. The storage element is used for storing results of the sigma-delta operations executed by the sigma-delta processing element. The sigma-delta circuit is used for executing a plurality of orders of sigma-delta operations through the coefficient generation element, the sigma-delta processing element and the storage element.

Abstract: A data transformation device including a pre-processing unit, a calculating unit and a post-processing unit is disclosed. The pre-processing unit performs a first pre-process with received image data to generate pre-processed image data, and performs a second pre-process with received result data to generate pre-processed result data. The calculating unit generates first calculated data and second calculated data according to the pre-processed image data and the pre-processed result data, by both a first calculating component and a second calculating component respectively. The post-processing unit performs a first post-process to generate the result data according to the first calculating data, and performs a second post-process to generate the image data according to the second calculating data.

Abstract: A data transformation method capable of saving numeral operations, the data transformation method includes encoding a plurality of digital data to generate a plurality of sets of byte data according to an encoding mode, determining a plurality of repetition patterns of the plurality of sets of byte data, processing shift operations on the plurality of sets of byte data to generate a plurality of sets of shifted byte data according to positions of the plurality of repetition patterns located in the plurality of sets of byte data, processing addition operations on the plurality of sets of shifted byte data.

Abstract: A method of optimal parameter adjustment includes randomly generating a first parameter group, setting each parameter into a device to detect a fitness function value corresponding to each parameter, copying parameters according to the fitness function value to form a second parameter group, randomly selecting parameter pairs from the second parameter group to implement a crossover method generating new parameter pairs to replace parameter pairs to form a third parameter group, and setting the third parameter group into the device to detect the fitness function value corresponding to each parameter and determining an optimal parameter according to the fitness function value.

Abstract: A sigma-delta circuit with time sharing architecture includes a coefficient generation element, a sigma-delta processing element, and a storage element. The coefficient generation element is used for generating coefficients for sigma-delta operations. The sigma-delta processing element is used for executing sigma-delta operations according to the coefficients generated by the coefficient generation element. The storage element is used for storing results of the sigma-delta operations executed by the sigma-delta processing element. The sigma-delta circuit is used for executing a plurality of orders of sigma-delta operations through the coefficient generation element, the sigma-delta processing element and the storage element.

Abstract: An image processing device includes a CSA accumulator, a first register, a CPA adder and a central processing unit. The CSA accumulator includes a first input for receiving a processing signal and a second input for receiving a previous result of the CSA accumulator. The first register includes an input coupled to the CSA accumulator and an output coupled to the second input end of the CSA accumulator. The CPA adder is coupled to the first register. The CPA adder is used for processing an addition operation on all carries outputted from the first register. The central processing unit includes an input coupled to the CPA adder and an output end for outputting an output signal comprising processed image measurement data.