Abstract: Aspects for increasing yield in an embedded memory device are described. With the aspects of the present invention, a cache is provided for a memory unit of an embedded memory device. Attempts to access a failed bit memory location in the memory unit are determined. When a failed memory bit location is being accessed, substitution of a memory location in the cache for the failed bit memory location occurs.

Abstract: A method and structure for a refresh operation with a low voltage of logic high in a computer memory structure is provided. The method and system includes first the precharging of a plurality of bit lines and a plurality of complementary bit lines to a voltage higher than the reference voltage. Then at least one of a plurality of word lines and at least one of a plurality of reference word lines are selected. Next, the sense amplifier is activated such that either the plurality of bit lines or the plurality of complementary bit lines discharges to a voltage of logic low. This discharge creates a voltage difference between the plurality of bit lines and the plurality of complementary bit lines. The resulting voltage on the bit lines is restored to the memory cells on the selected word lines. Then, the plurality of bit lines and the plurality of complementary bit lines are restored to the reference voltage. This method and structure allows the use of a logic high voltage lower than 2.

Abstract: Aspects for self bootstrapping word-line driver circuitry are provided. In a circuit aspect, a word-line driver circuit for a memory cell in a semiconductor memory includes a signal input means, the signal input means comprising a first plurality of transistors, the first plurality of transistors receiving an input voltage signal higher than a voltage supply signal of the semiconductor memory. The circuit further includes a signal output means, the signal output means comprising a second plurality of transistors coupled to the first plurality of transistors and providing an output drive signal sufficient for the memory cell.

Abstract: Circuit, method, and system aspects for achieving redundancy circuitry programming in semiconductor memory are provided. Through these aspects, utilization of a circuit including a logic mechanism for receiving an enable signal and an address signal, a switching mechanism coupled to the logic mechanism for controlling delivery of the address signal, and a fuse mechanism coupled to the logic mechanism for allowing selective address programming responsive to the address signal in order to produce a desired logic level for a redundant address output signal occurs to form an address programming circuit. Further, selective input of an enable signal to the address programming circuit provides control of the address programming circuit to produce a desired logic level output. Additionally, integration of a plurality of the address programming circuits to form a redundancy programming circuit is achieved with each address programming circuit corresponding to one bit of an input address signal.