Abstract: A method for backing up a configuration file of a computer device is implemented by a baseboard management controller, and includes steps of: mounting a first partition, a second partition and a third partition of a flash memory storage device of the computer device; storing a copy of the configuration file in at least one of the first partition, the second partition and the third partition that has been mounted successfully as a backup; running an operating system stored in the flash memory storage device; and neither reading nor writing to the third partition while running the OS.

Abstract: A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.

Abstract: A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill, wherein the first liner layer surrounds the conductive fill.

Abstract: A plating apparatus for electroplating a wafer includes a housing defining a plating chamber for housing a plating solution. A voltage source of the apparatus has a first terminal having a first polarity and a second terminal having a second polarity different than the first polarity. The first terminal is electrically coupled to the wafer. An anode is within the plating chamber, and the second terminal is electrically coupled to the anode. A membrane support is within the plating chamber and over the anode. The membrane support defines apertures, wherein in a first zone of the membrane support a first aperture-area to surface-area ratio is a first ratio, and in a second zone of the membrane support a second aperture-area to surface-area ratio is a second ratio, different than the first ratio.

Abstract: An antenna structure includes a ground element, a feeding radiation element, a first radiation element, a second radiation element, a first coupling branch, and a dielectric substrate. The feeding radiation element has a feeding point. The first radiation element is coupled to the feeding radiation element. The second radiation element is coupled to the feeding radiation element. The second radiation element and the first radiation element substantially extend in opposite directions. The first coupling branch is coupled to a first grounding point on the ground element. The first coupling branch extends across the first radiation element. The first coupling branch includes a first coil portion and a first connection portion.

Abstract: The present disclosure discloses a transceiver apparatus having self-calibration mechanism that includes a signal transmission path, a signal receiving path, a path switching circuit, a transceiver circuit and a self-calibration circuit. The path switching circuit includes a switch to switch a connection relation among an antenna, the signal transmission path and the signal receiving path. The transceiver circuit is coupled to the signal transmission path and the signal receiving path. The self-calibration circuit controls the transceiver circuit to transmit a transmission signal through the signal transmission path to the path switching circuit and receives a leakage signal generated according to the transmission signal through the signal receiving path, so as to perform a self-calibration process on the transceiver circuit based on the transmission signal and the leakage signal. The leakage signal has a leakage signal strength larger than a predetermined level.

Abstract: The application discloses a method, for building an oscillator frequency adjustment lookup table in a transceiver, wherein the transceiver generates a clock according to a crystal oscillator external to the transceiver for transceiving data. The transceiver includes adjustable capacitor arrays assembly connected to the crystal oscillator, wherein when an equivalent capacitance of the adjustable capacitor assembly is a reference value, the crystal oscillator has a reference frequency, and when the equivalent capacitance changes relative to the reference value, the crystal oscillator correspondingly has a frequency offset relative to the reference frequency. The method includes: performing an interpolation operation according to a first value, a second value, and a third value of the equivalent capacitance, and the corresponding frequency variations, so as to obtain the frequency variations corresponding to a first sub-value between the first value and the second values.

Abstract: The application discloses a method, for building an oscillator frequency adjustment lookup table in a transceiver, wherein the transceiver generates a clock according to a crystal oscillator external to the transceiver for transceiving data. The transceiver includes adjustable capacitor arrays assembly connected to the crystal oscillator, wherein when an equivalent capacitance of the adjustable capacitor assembly is a reference value, the crystal oscillator has a reference frequency, and when the equivalent capacitance changes relative to the reference value, the crystal oscillator correspondingly has a frequency offset relative to the reference frequency. The method includes: performing an interpolation operation according to a first value, a second value, and a third value of the equivalent capacitance, and the corresponding frequency variations, so as to obtain the frequency variations corresponding to a first sub-value between the first value and the second values.