Abstract: A method of measuring a surface structure of a display device is provided. The display device includes first and second substrates, first and second patterned light-shielding layers, and first and second pixel units. The first patterned light-shielding layer disposed on a surface of the first substrate includes first openings. The second patterned light-shielding layer disposed on the surface of the first substrate includes second openings. The first pixel unit includes first and second protrusions. The first protrusion correspondingly covers the first openings and a portion of the first patterned light-shielding layer. The second protrusion is disposed on and directly contacted with the first and second patterned light-shielding layers. The second pixel unit includes a third protrusion correspondingly covering the second openings and a portion of the second patterned light-shielding layer, wherein sizes of the second openings are smaller than sizes of the first openings.

Abstract: A method of measuring a surface structure of a display device is provided. The display device includes first and second substrates, first and second patterned light-shielding layers, and first and second pixel units. The first patterned light-shielding layer disposed on a surface of the first substrate includes first openings. The second patterned light-shielding layer disposed on the surface of the first substrate includes second openings. The first pixel unit includes first and second protrusions. The first protrusion correspondingly covers the first openings and a portion of the first patterned light-shielding layer. The second protrusion is disposed on and directly contacted with the first and second patterned light-shielding layers. The second pixel unit includes a third protrusion correspondingly covering the second openings and a portion of the second patterned light-shielding layer, wherein sizes of the second openings are smaller than sizes of the first openings.

Abstract: A display device and a method of measuring a surface structure of the same are provided. The display device includes first and second substrates, first and second patterned light-shielding layers, and first and second pixel units. The first patterned light-shielding layer disposed on a surface of the first substrate includes first openings. The second patterned light-shielding layer disposed on the surface of the first substrate in the first patterned light-shielding layer includes second openings. The first pixel unit includes first and second protrusions. The first protrusion correspondingly covers the first openings and a portion of the first patterned light-shielding layer. The second protrusion is disposed in the first and second patterned light-shielding layers. The second pixel unit includes a third protrusion correspondingly covering the second openings and a portion of the second patterned light-shielding layer, wherein sizes of the second openings are smaller than sizes of the first openings.

Abstract: A display device and a method of measuring a surface structure of the same are provided. The display device includes first and second substrates, first and second patterned light-shielding layers, and first and second pixel units. The first patterned light-shielding layer disposed on a surface of the first substrate includes first openings. The second patterned light-shielding layer disposed on the surface of the first substrate in the first patterned light-shielding layer includes second openings. The first pixel unit includes first and second protrusions. The first protrusion correspondingly covers the first openings and a portion of the first patterned light-shielding layer. The second protrusion is disposed in the first and second patterned light-shielding layers. The second pixel unit includes a third protrusion correspondingly covering the second openings and a portion of the second patterned light-shielding layer, wherein sizes of the second openings are smaller than sizes of the first openings.

Abstract: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line region through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. Each of the plurality of active circuit die areas has four sides. An overcoat covers both the active circuit die areas and the dicing line region. An inter-layer dielectric layer is disposed underneath the overcoat. A reinforcement structure includes a plurality of holes formed within the dicing line region. The plurality of holes are formed by etching through the overcoat into the inter-layer dielectric layer and are disposed along the four sides of each active circuit die area. A die seal ring is disposed in between the active circuit chip area and the reinforcement structure.

Abstract: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line region through which the plurality of active circuit die areas are separated from each other, wherein each of the plurality of active circuit die areas has substantially four corners. An overcoat is deposited to cover both the active circuit die areas and the dicing line region. A first trench is formed by etching through the overcoat and disposed merely around the four corners of each active circuit die area. A reinforcing second trench is etched into the overcoat and is disposed in proximity to the first trench. A die seal ring is disposed in between the active circuit chip area and the first trench.

Abstract: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line region through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. Each of the plurality of active circuit die areas has four sides. An overcoat covers both the active circuit die areas and the dicing line region. An inter-layer dielectric layer is disposed underneath the overcoat. A reinforcement structure includes a plurality of holes formed within the dicing line region. The plurality of holes are formed by etching through the overcoat into the inter-layer dielectric layer and are disposed along the four sides of each active circuit die area. A die seal ring is disposed in between the active circuit chip area and the reinforcement structure.

Abstract: A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.

Abstract: The present invention provides a novel probe tip suited for flip-chip packaging process. The probe tip comprises a needle body; and a stop cylinder having a recess for fittingly accommodating the needle body therein, the needle body being electrically connected to the stop cylinder via a resilient conductive material. The stop cylinder has an annual flat bottom surrounding the needle body for pressing a protruding probe mark on a metal pad scratched by the needle body.

Abstract: The present invention provides a novel probe tip suited for flip-chip packaging process. The probe tip comprises a needle body; and a stop cylinder having a recess for fittingly accommodating the needle body therein, the needle body being electrically connected to the stop cylinder via a resilient conductive material. The stop cylinder has an annual flat bottom surrounding the needle body for pressing a protruding probe mark on a metal pad scratched by the needle body.

Abstract: A solder bump structure and laser repair process for memory device include forming a first dielectric layer on a bump pad of a semiconductor wafer. After that, the first dielectric layer is etched to form a contact hole and to expose portions of the bump pad. A second dielectric layer is then formed on a surface of the semiconductor wafer outside of the contact hole. An under bump metallurgy (UBM) process is performed to form a metal layer on a surface of the contact hole, and a solder bump is formed on the metal layer. Finally, the laser repair process for memory device is completed.

Abstract: The present invention provides a novel probe tip suited for flip-chip packaging process. The probe tip comprises a needle body; and a stop cylinder having a recess for fittingly accommodating the needle body therein, the needle body being electrically connected to the stop cylinder via a resilient conductive material. The stop cylinder has an annual flat bottom surrounding the needle body for pressing a protruding probe mark on a metal pad scratched by the needle body.

Abstract: An improved microelectronic package is disclosed. The microelectronic package includes a packaging substrate having an upper surface and an underside. At least one chip is mounted on the upper surface of the packaging substrate. A plurality of ball grid array (BGA) solder balls are mounted at the underside of the packaging substrate. At least one RC passive component is disposed underneath the chip. The chip may be mounted on predetermined position on the upper surface of the packaging substrate with solder bumps by using Flip-Chip (FC) assembly method. According to one aspect of the present invention, the RC passive component is disposed between the BGA solder balls. According to one aspect of the present invention, the RC passive component is an adjustable resist having a plurality of bumps formed thereon, and wherein two metal trace lines, which correspond to two bumps of the plural bumps, are provided on the underside of the packaging substrate.

Abstract: A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.

Abstract: A solder bump structure and laser repair process for memory device include forming a first dielectric layer on a bump pad of a semiconductor wafer. After that, the first dielectric layer is etched to form a contact hole and to expose portions of the bump pad. A second dielectric layer is then formed on a surface of the semiconductor wafer outside of the contact hole. An under bump metallurgy (UBM) process is performed to form a metal layer on a surface of the contact hole, and a solder bump is formed on the metal layer. Finally, the laser repair process for memory device is completed.