Abstract: An RF receiver and an RF transmitter, which are integrated in a single substrate, are operable to share a single reconfigurable filter to perform RF receiver filtering and RF transmitter filtering. The reconfigurable filter is configured to operate as a bandpass filter such as an image rejection bandpass filter for receiving RF signals by the RF receiver. The reconfigurable filter operates as a low pass filter for transmitting RF signals by the RF transmitter. The reconfigurable filter is configured to operate in a RF receiver filtering mode or a RF transmitter filtering mode, respectively. The reconfigurable filter is enabled to share configurable circuit components of the radio transceiver in both the radio frequency receiver filtering mode and the radio frequency transmitter filtering mode. The reconfigurable filter transitions between the radio frequency receiver filtering mode and the radio frequency transmitter filtering mode via reconfiguring the shared configurable circuit components.

Abstract: An RF receiver and an RF transmitter, which are integrated in a single substrate, are operable to share a single reconfigurable filter to perform RF receiver filtering and RF transmitter filtering. The reconfigurable filter is configured to operate as a bandpass filter such as an image rejection bandpass filter for receiving RF signals by the RF receiver. The reconfigurable filter operates as a low pass filter for transmitting RF signals by the RF transmitter. The reconfigurable filter is configured to operate in a RF receiver filtering mode or a RF transmitter filtering mode, respectively. The reconfigurable filter is enabled to share configurable circuit components of the radio transceiver in both the radio frequency receiver filtering mode and the radio frequency transmitter filtering mode. The reconfigurable filter transitions between the radio frequency receiver filtering mode and the radio frequency transmitter filtering mode via reconfiguring the shared configurable circuit components.

Abstract: An RF receiver and an RF transmitter, which are integrated in a single substrate, are operable to share a single reconfigurable filter to perform RF receiver filtering and RF transmitter filtering. The reconfigurable filter is configured to operate as a bandpass filter such as an image rejection bandpass filter for receiving RF signals by the RF receiver. The reconfigurable filter operates as a low pass filter for transmitting RF signals by the RF transmitter. The reconfigurable filter is configured to operate in a RF receiver filtering mode or a RF transmitter filtering mode, respectively. The reconfigurable filter is enabled to share configurable circuit components of the radio transceiver in both the radio frequency receiver filtering mode and the radio frequency transmitter filtering mode. The reconfigurable filter transitions between the radio frequency receiver filtering mode and the radio frequency transmitter filtering mode via reconfiguring the shared configurable circuit components.

Abstract: A phase locked loop includes a detection module, a control conversion module, a controlled oscillation module, a divider module, and a power distribution module. The detection module is operably coupled to produce a difference signal based on a difference between a reference oscillation and a feedback oscillation. The control conversion module is operably coupled to convert the difference signal into a control signal. The controlled oscillation module is operably coupled to produce an output oscillation based on the control signal. The divider module is operably coupled to produce the feedback oscillation based on the output oscillation. The power distribution module is operably coupled to receive a supply voltage and to provide an individual supply voltage to at least one of the detection module, the control conversion module, the controlled oscillation module, and the divider module to optimize at least one of performance and power consumption of the phase locked loop.

Abstract: A low noise divider module includes a divider chain and a retiming module. The divider chain includes a plurality of cascaded dividers and a plurality of load logic gates. The plurality of cascaded dividers are operably coupled to divide an input oscillation by a divider value, which is programmable, to produce a divided output oscillation based on the load signals provided by the logic gates. The retiming module includes a duty cycle module and a jitter reduction module. The duty cycle module is coupled to produce a duty cycle controlled output oscillation based on a representation of the divided output oscillation produced by the divider chain in accordance with a duty cycle setting signal. The jitter reduction module is operably coupled to produce a low jitter output oscillation from the duty cycle controlled output oscillation based on the input oscillation and the duty cycle setting signal.

Abstract: A linear fractional-N synthesizer includes phase and frequency detection module, a charge pump circuit, a loop filter, a voltage controlled oscillator, and a fractional-N divider. The phase and frequency detection module is operably coupled to produce a charge up signal, a charge down signal, or an off signal based on a phase difference and/or a frequency difference between a reference oscillation and a feedback oscillation. The charge pump circuit is operably coupled to produce a positive current when the charge up signal is received, a negative current when the charge down signal is received, and a non-zero offset current when the off signal is received. The charge pump includes a resistor and a control module. The resistor provides the non-zero offset current and the control module maintains the non-zero offset current at a substantially constant value.

Abstract: A signal power detector includes an input coupling circuit, a rectifying operational amplifier, a comparator, and a charge pump. The input coupling circuit is operably coupled to receive a signal and to convert the signal into a first input and a rectifying input. The rectifying operational amplifier is operably coupled to receive the first input and the rectifying input and to produce therefrom a rectified output signal that represents a peak of the received signal. The comparator is operably coupled to compare the peak value of the signal with an output peak value to produce a comparison value. The charge pump operably coupled to convert the comparison value into a corresponding current that represents the output peak value.

Abstract: A signal power detector includes an input coupling circuit a rectifying operational amplifier, and a charge pump. The input coupling circuit is operably coupled to receive a signal and to convert the signal into a first input and a rectifying input. The rectifying operational amplifier is operably coupled to receive the first input and the rectifying input and to produce therefrom a rectified output signal that represents a peak of the received signal. The charge pump converts the rectified output into a corresponding current, wherein the corresponding current represents power of the signal.

Abstract: A phase locked loop that includes such a loop filter, the phase locked loop includes a difference detector, programmable charge pump, fixed loop filter, voltage controlled oscillator and adjustable divider module. The difference detector is operably coupled to determine a different signal based on differences in phase and/or frequency between a reference oscillation and a feedback oscillation. The programmable charge pump is operably coupled to generate a charge current based on the difference signal and a scaling signal. The fixed loop filter is operably coupled to convert the charge current into a control voltage. The voltage controlled oscillator generates an output oscillation based on the control voltage and the adjustable divider module generates the feedback oscillation based on the output oscillation and a divider value. The scaling module is operably coupled to produce the scaling signal based on the selected divider.

Abstract: A signal power detector includes an input coupling circuit a rectifying operational amplifier, and a charge pump. The input coupling circuit is operably coupled to receive a signal and to convert the signal into a first input and a rectifying input. The rectifying operational amplifier is operably coupled to receive the first input and the rectifying input and to produce therefrom a rectified output signal that represents a peak of the received signal. The charge pump converts the rectified output into a corresponding current, wherein the corresponding current represents power of the signal.

Abstract: A signal power detector includes an input coupling circuit and a rectifying operational amplifier. The input coupling circuit is operably coupled to receive a signal and to convert the signal into a first input and a rectifying input. The rectifying operational amplifier is operably coupled to receive the first input and the rectifying input and to produce therefrom a rectified output signal that represents a peak of the received signal.

Abstract: A signal power detector includes an input coupling circuit, a rectifying operational amplifier, a comparator, and a charge pump. The input coupling circuit is operably coupled to receive a signal and to convert the signal into a first input and a rectifying input. The rectifying operational amplifier is operably coupled to receive the first input and the rectifying input and to produce therefrom a rectified output signal that represents a peak of the received signal. The comparator is operably coupled to compare the peak value of the signal with an output peak value to produce a comparison value. The charge pump operably coupled to convert the comparison value into a corresponding current that represents the output peak value.

Abstract: A signal power detector includes an input coupling circuit and a rectifying operational amplifier. The input coupling circuit is operably coupled to receive a signal and to convert the signal into a first input and a rectifying input. The rectifying operational amplifier is operably coupled to receive the first input and the rectifying input and to produce therefrom a rectified output signal that represents a peak of the received signal.

Abstract: A phase locked loop that includes such a loop filter, the phase locked loop includes a difference detector, programmable charge pump, fixed loop filter, voltage controlled oscillator and adjustable divider module. The difference detector is operably coupled to determine a different signal based on differences in phase and/or frequency between a reference oscillation and a feedback oscillation. The programmable charge pump is operably coupled to generate a charge current based on the difference signal and a scaling signal. The fixed loop filter is operably coupled to convert the charge current into a control voltage. The voltage controlled oscillator generates an output oscillation based on the control voltage and the adjustable divider module generates the feedback oscillation based on the output oscillation and a divider value. The scaling module is operably coupled to produce the scaling signal based on the selected divider.

Abstract: A low noise divider module includes a divider chain and a retiming module. The divider chain includes a plurality of cascaded dividers and a plurality of load logic gates. The plurality of cascaded dividers are operably coupled to divide an input oscillation by a divider value, which is programmable, to produce a divided output oscillation based on the load signals provided by the logic gates. The retiming module includes a duty cycle module and a jitter reduction module. The duty cycle module is coupled to produce a duty cycle controlled output oscillation based on a representation of the divided output oscillation produced by the divider chain in accordance with a duty cycle setting signal. The jitter reduction module is operably coupled to produce a low jitter output oscillation from the duty cycle controlled output oscillation based on the input oscillation and the duty cycle setting signal.