Abstract: The disclosure provides an integrated circuit and an operation method and an inspection method thereof. The integrated circuit includes a one-time programmable (OTP) memory, an identifier generation circuit, and a memory controller. The identifier generation circuit generates a random number, and performs an error-detection-code encoding operation on the random number to generate an identifier with an error-detection code. The memory controller writes the identifier generated by the identifier generation circuit into the OTP memory. The identifier generation circuit reads the identifier from the OTP memory through the memory controller, and performs an error-detection-code decoding operation on the identifier provided by the memory controller to determine whether an error of the identifier from the OTP memory is correctable. When it is determined that the error of the identifier from the OTP memory is not correctable, the writing of the identifier is deemed failed.

Abstract: A board to board connector includes a first male connector and a second male connector. The first male connector includes a first number of pins. The second male connector is aligned with the first male connector and includes a second number of pins. The first male connector is configured to be removably electrically coupled to a first female connector including a third number of pins equal to the first number and the second male connector is configured to be removably electrically coupled to a second female connector including a fourth number of pins equal to the second number. The first male connector and the second male connector are also configured to be removably electrically coupled to a single third female connector including a fifth number of pins equal to the first number plus the second number.

Abstract: The disclosure provides an integrated circuit and an operation method and an inspection method thereof. The integrated circuit includes a one-time programmable (OTP) memory, an identifier generation circuit, and a memory controller. The identifier generation circuit generates a random number, and performs an error-detection-code encoding operation on the random number to generate an identifier with an error-detection code. The memory controller writes the identifier generated by the identifier generation circuit into the OTP memory. The identifier generation circuit reads the identifier from the OTP memory through the memory controller, and performs an error-detection-code decoding operation on the identifier provided by the memory controller to determine whether an error of the identifier from the OTP memory is correctable. When it is determined that the error of the identifier from the OTP memory is not correctable, the writing of the identifier is deemed failed.

Abstract: An example apparatus to retain a computer power brick in a power brick holder includes a plate and a positioning mechanism removably attached at any of a plurality of positions on the plate. The positioning mechanism is attached at a preset position on the plate based on a size of the power brick.

Abstract: An adaptive serial general-purpose input output (ASGPIO) interface and a signal receiver thereof suitable for a secure control module (SCM) are provided. The ASGPIO interface includes a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transmitted data and provides previously transmitted data. The comparator receives currently transmitted data and receives the previously transmitted data. In a first mode, the comparator compares the previously transmitted data with the currently transmitted data to generate a data variation information. The encoder, in the first mode, generates at least one index value and a corresponding instruction signal according to the data variation information. The signal transmitter sends the at least one index value as a serial signal and the instruction signal to a signal receiver.

Abstract: A solar cell includes a silicon substrate, a passivation layer, a first protection layer, a second protection layer, and a third protection layer. The material of the passivation layer is aluminum oxide, and the passivation layer is on the lower surface of the silicon substrate. The material of the first protection layer is silicon oxynitride, and the first protection layer is on a surface of the passivation layer opposite to the silicon substrate. The material of the second protection layer is silicon nitride, and the second protection layer is on a surface of the first protection layer opposite to the passivation layer. The material of the third protection layer is silicon oxynitride or silicon oxide, and the third protection layer is on a surface of the second protection layer opposite to the first protection layer.

Abstract: An example ventilation system for a computing device includes: a cover slidably engageable with a housing of the computing device to a closed position defining an internal space of the computing device, the cover having first ventilation holes; a system mesh slidably engaged with the cover, the system mesh having second ventilation holes; and a stopper disposed in the internal space of the computing device, the stopper to stop the system mesh at a predefined position when the cover is engaged with the housing in the closed position, wherein the first ventilation holes and the second ventilation holes overlap to define system ventilation holes for the computing device.

Abstract: A signal transceiving system and a signal receiver thereof are provided. The signal transceiving system includes a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transmitted data and provides previously transmitted data. The comparator receives currently transmitted data and receives the previously transmitted data. The comparator compares, in a first mode, the previously transmitted data with the currently transmitted data to generate a data variation information. The encoder generates, in the first mode, at least one index value and a corresponding instruction signal according to the data variation information. The signal transmitter sends the at least one index value which is a serial signal and the instruction signal to a signal receiver.

Abstract: A signal transceiving system and a signal receiver thereof are provided. The signal transceiving system includes a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transmitted data and provides previously transmitted data. The comparator receives currently transmitted data and receives the previously transmitted data. The comparator compares, in a first mode, the previously transmitted data with the currently transmitted data to generate a data variation information. The encoder generates, in the first mode, at least one index value and a corresponding instruction signal according to the data variation information. The signal transmitter sends the at least one index value which is a serial signal and the instruction signal to a signal receiver.

Abstract: An adaptive serial general-purpose input output (ASGPIO) interface and a signal receiver thereof suitable for a secure control module (SCM) are provided. The ASGPIO interface includes a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transmitted data and provides previously transmitted data. The comparator receives currently transmitted data and receives the previously transmitted data. In a first mode, the comparator compares the previously transmitted data with the currently transmitted data to generate a data variation information. The encoder, in the first mode, generates at least one index value and a corresponding instruction signal according to the data variation information. The signal transmitter sends the at least one index value as a serial signal and the instruction signal to a signal receiver.

Abstract: An example apparatus to retain a computer power brick in a power brick holder includes a plate and a positioning mechanism removably attached at any of a plurality of positions on the plate. The positioning mechanism is attached at a preset position on the plate based on a size of the power brick.

Abstract: A board to board connector includes a first male connector and a second male connector. The first male connector includes a first number of pins. The second male connector is aligned with the first male connector and includes a second number of pins. The first male connector is configured to be removably electrically coupled to a first female connector including a third number of pins equal to the first number and the second male connector is configured to be removably electrically coupled to a second female connector including a fourth number of pins equal to the second number. The first male connector and the second male connector are also configured to be removably electrically coupled to a single third female connector including a fifth number of pins equal to the first number plus the second number.

Abstract: Example thermal modules are disclosed. An example thermal module for use with an electronic device includes a first heatsink defining a first airflow exit. The first heatsink including a first set of fins having a first height and a second set of fins having a second height. The second height being less than the first height. The second set of fins being adjacent the first airflow exit. A second heatsink defines a second airflow exit. The second heatsink is spaced from the first heatsink to form a gap therebetween. The second heatsink is thermally coupled to the first heatsink via a heat pipe.

Abstract: A time-of-flight (ToF) system disclosed herein provides a method of a method of separating a direct component of light collected by a time of flight (ToF) detector from a global component of light collected by the ToF detector, the method comprising acquiring three or more images represented by three or more matrices in response to illuminating a target with a light source using a first spatial pattern at three or more different modulation frequencies, acquiring an additional image represented by an additional matrix in response to illuminating the target with the light source using a second spatial pattern, the second spatial pattern being different than the first spatial pattern, and determining one or more parameters of the direct component of light and the global component of light based on analysis of the three or more matrices and the additional matrix.

Abstract: Example thermal modules are disclosed. An example thermal module for use with an electronic device includes a first heatsink defining a first airflow exit. The first heatsink including a first set of fins having a first height and a second set of fins having a second height. The second height being less than the first height. The second set of fins being adjacent the first airflow exit. A second heatsink defines a second airflow exit. The second heatsink is spaced from the first heatsink to form a gap therebetween. The second heatsink is thermally coupled to the first heatsink via a heat pipe.

Abstract: A time-of-flight (ToF) system disclosed herein provides a method of a method of separating a direct component of light collected by a time of flight (ToF) detector from a global component of light collected by the ToF detector, the method comprising acquiring three or more images represented by three or more matrices in response to illuminating a target with a light source using a first spatial pattern at three or more different modulation frequencies, acquiring an additional image represented by an additional matrix in response to illuminating the target with the light source using a second spatial pattern, the second spatial pattern being different than the first spatial pattern, and determining one or more parameters of the direct component of light and the global component of light based on analysis of the three or more matrices and the additional matrix.

Abstract: A time-of-flight (ToF) camera is configured to operate in a manner that reduces power consumption of the ToF camera. For a key frame, a key-frame depth image is generated based on a plurality of sets of key-frame IR images. Each set of key-frame IR images is acquired using a different modulation frequency of active IR light. For a P-frame after the key frame, a P-frame depth image is generated based on a set of P-frame IR images acquired using a single modulation frequency of active IR light.

Abstract: A time-of-flight (ToF) camera is configured to operate in a manner that reduces power consumption of the ToF camera. For a key frame, a key-frame depth image is generated based on a plurality of sets of key-frame IR images. Each set of key-frame IR images is acquired using a different modulation frequency of active IR light. For a P-frame after the key frame, a P-frame depth image is generated based on a set of P-frame IR images acquired using a single modulation frequency of active IR light.

Abstract: An image processing apparatus is disclosed, which comprises a rasterization engine, a texture mapping module and a destination buffer. The rasterization engine receives a group of vertices from a vertex list and performs polygon rasterization operations for a point within the group of vertices forming a polygon to generate texture coordinates for each camera image. The vertex list comprises a plurality of vertices with their data structures. The texture mapping module texture maps texture data from each camera image according to its texture coordinates to generate a sample value for each camera image. The destination buffer is coupled to the texture mapping module and stores the panoramic image. Here, the data structures define a mapping between the panoramic image and the camera images.

Abstract: A power measurement circuit is disclosed. The power measurement circuit comprises a sampling register, a latch generator, an accumulation unit, a calculation unit and an output register. The sampling register samples an input signal based on a sampling clock to generate a binary digit. The latch generator generates a latch signal based on the sampling clock and a measurement interval. The accumulation unit accumulates the binary digit based on the latch signal to generate a sum value. The calculation unit calculates an ON-phase rate of the input signal according to the sum value and the measurement interval. The output register stores a power consumption value according to the ON-phase rate of the input signal.