Abstract: A system for data transfer between different clock domains, and for efficiently obtaining the status of a memory device utilized during the process of data transfer. The different clock domains include a first clock domain controlled by a first frequency and a second clock domain controlled by a second frequency different from the first frequency. The system features a first counter circuitry operating at the first clock frequency which increments in response to a write control signal. The system further features first and second sync circuitries for translating write and read signals, and a second counter circuitry operating at the second clock frequency, which decrements in response to the read control signal. In addition, the first circuitry decrements in response to the read signal while the second circuitry increments in response to a write signal. In this manner, the first and second counter circuitries reflect the status of the memory device used for buffering data during the data transfer.

Abstract: A system for data transfer between different clock domains, and for efficiently obtaining the status of a memory device utilized during the process of data transfer. The different clock domains include a first clock domain controlled by a first frequency and a second clock domain controlled by a second frequency different from the first frequency. The system features a first counter circuitry operating at the first clock frequency which increments in response to a write control signal. The system further features first and second sync circuitries for translating write and read signals, and a second counter circuitry operating at the second clock frequency, which decrements in response to the read control signal. In addition, the first circuitry decrements in response to the read signal while the second circuitry increments in response to a write signal. In this manner, the first and second counter circuitries reflect the status of the memory device used for buffering data during the data transfer.