Patents by Inventor Hung-Pin Lu

Hung-Pin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230009981
    Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.
    Type: Application
    Filed: February 16, 2022
    Publication date: January 12, 2023
    Inventors: Cheng-Wei CHANG, Chia-Hung CHU, Hsu-Kai CHANG, Sung-Li WANG, Kuan-Kan HU, Shuen-Shin LIANG, Kao-Feng LIN, Hung Pin LU, Yi-Ying LIU, Chuan-Hui SHEN
  • Patent number: 11457850
    Abstract: A neural-signal amplifier includes an amplifier, a switched-capacitor circuit-input unit, a switched-capacitor feedback-circuit unit, and a switched-capacitor circuit-output unit. Each of the switched-capacitor circuit-input unit, the switched-capacitor feedback-circuit unit, and the switched-capacitor circuit-output unit includes a plurality of differential switches, a plurality of common mode switches, and a plurality of capacitors. By controlling the switches to turn on or performing the switched-capacitor operation, the neural-signal amplifier is controlled to suppress the DC drift and reconstruct the DC input of the common-mode power supply.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: October 4, 2022
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Hung-Pin Lu, Po-Tsang Huang, Wei Hwang
  • Publication number: 20200178823
    Abstract: A neural-signal amplifier includes an amplifier, a switched-capacitor circuit-input unit, a switched-capacitor feedback-circuit unit, and a switched-capacitor circuit-output unit. Each of the switched-capacitor circuit-input unit, the switched-capacitor feedback-circuit unit, and the switched-capacitor circuit-output unit includes a plurality of differential switches, a plurality of common mode switches, and a plurality of capacitors. By controlling the switches to turn on or performing the switched-capacitor operation, the neural-signal amplifier is controlled to suppress the DC drift and reconstruct the DC input of the common-mode power supply.
    Type: Application
    Filed: December 5, 2019
    Publication date: June 11, 2020
    Inventors: Hung-Pin LU, Po-Tsang HUANG, Wei HWANG
  • Patent number: 10153203
    Abstract: A method includes forming an Inter-layer Dielectric (ILD) having a portion at a same level as a metal gate of a transistor. The ILD and the metal gate are parts of a wafer. The ILD is etched to form a contact opening. The wafer is placed into a PVD tool, with a metal target in the PVD tool. The metal target has a first spacing from a magnet over the metal target, and a second spacing from the wafer. A ratio of the first spacing to the second spacing is greater than about 0.02. A metal layer is deposited on the wafer, with the metal layer having a bottom portion in the contact opening, and a sidewall portion in the contact opening. An anneal is performed to react the bottom portion of the metal layer with the source/drain region to form a silicide region.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Wang, Yu-Ting Lin, Hung-Chang Hsu, Hsiao-Ping Liu, Hung Pin Lu, Yuan Wen Lin
  • Publication number: 20180151429
    Abstract: A method includes forming an Inter-layer Dielectric (ILD) having a portion at a same level as a metal gate of a transistor. The ILD and the metal gate are parts of a wafer. The ILD is etched to form a contact opening. The wafer is placed into a PVD tool, with a metal target in the PVD tool. The metal target has a first spacing from a magnet over the metal target, and a second spacing from the wafer. A ratio of the first spacing to the second spacing is greater than about 0.02. A metal layer is deposited on the wafer, with the metal layer having a bottom portion in the contact opening, and a sidewall portion in the contact opening. An anneal is performed to react the bottom portion of the metal layer with the source/drain region to form a silicide region.
    Type: Application
    Filed: August 1, 2017
    Publication date: May 31, 2018
    Inventors: Yu-Sheng Wang, Yu-Ting Lin, Hung-Chang Hsu, Hsiao-Ping Liu, Hung Pin Lu, Yuan Wen Lin
  • Patent number: 5870004
    Abstract: The frequency of an integrated oscillator is held constant by using temperature compensation to compensate for the component variations due to temperature variations. A voltage controlled oscillator, which has temperature dependent components, is compensated with a temperature dependent control voltage. The frequency of many kinds of oscillators such as a relaxation oscillators and ring oscillators can be held constant when the operating current is held constant. The operating current is often derived from a current source, which is a voltage to current converter with a current equal to the ratio of a control voltage to a resistance. Since semiconductor resistance has a positive temperature coefficient is used to obtain a temperature invariant current source. The positive temperature coefficient is obtained with the difference junction voltage of two forward-biased pn junction voltages. The magnitude can be controlled by junction areas of the two junctions. The magnitude can also be amplified.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: February 9, 1999
    Assignee: Utron Technology Inc.
    Inventor: Hung-Pin Lu