Abstract: A time-division mechanism that a source station uses a proprietary frame for notifying switching from a normal bandwidth operation to a narrow bandwidth operation to at least one destination station in a wireless communication system, and uses a protection frame to reserve the service period for the narrow bandwidth operation without the interference from the normal bandwidth operation, wherein the service period of the narrow bandwidth operation is indicated in the protection frame.

Abstract: A time-division mechanism that a source station uses a proprietary frame for notifying switching from a normal bandwidth operation to a narrow bandwidth operation to at least one destination station in a wireless communication system, and uses a protection frame to reserve the service period for the narrow bandwidth operation without the interference from the normal bandwidth operation, wherein the service period of the narrow bandwidth operation is indicated in the protection frame.

Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.

Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.