Patents by Inventor Hung-Ping LEE
Hung-Ping LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11936238Abstract: An uninterruptible power apparatus is coupled between a power grid and a load. The uninterruptible power apparatus includes a bypass path, a power conversion module, and a control module. The bypass path is coupled to the power grid through a grid terminal, and coupled to the load through a load terminal. The control module turns off a first thyristor and a second thyristor by injecting a second voltage into the load terminal during a forced commutation period. The control module calculates a magnetic flux offset amount based on an error amount between the second voltage and a voltage command, and provides a compensation command in response to the magnetic flux offset amount. The control module controls the DC/AC conversion circuit to provide a third voltage to the load terminal based on the compensation command and the voltage command.Type: GrantFiled: June 15, 2022Date of Patent: March 19, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Hsin-Chih Chen, Hung-Chieh Lin, Chao-Lung Kuo, Yi-Ping Hsieh, Chien-Shien Lee
-
Publication number: 20240009702Abstract: A manufacturing method of a wafer level ultrasonic device includes: forming a first piezoelectric material layer, a first electrode material layer, a second piezoelectric material layer, and a second electrode material layer in sequence on a substrate; removing parts of those layers to form an ultrasonic element including a first electrode and a second electrode; forming a first protective layer on the ultrasonic element, and forming a first through hole and a second through hole exposing a part of the first electrode and a part of the second electrode; forming a first conductive layer and a second conductive layer on the first protective layer and connecting to the first electrode and the second electrode; forming a second protective layer; and connecting a base with an opening and the second protective layer in a vacuum environment to form a closed cavity.Type: ApplicationFiled: September 20, 2023Publication date: January 11, 2024Inventors: Yi-Hsiang Chiu, Hung-Ping Lee
-
Publication number: 20240009703Abstract: A wafer level ultrasonic device includes a composite layer, a first conductive layer, a second conductive layer, a base, a first electrical connection region, and a second electrical connection region. The composite layer includes an ultrasonic element and a protective layer. The ultrasonic element includes a first electrode and a second electrode. The protective layer has a first connecting channel and a second connecting channel respectively corresponding to the first electrode and the second electrode. The first conductive layer and the second conductive layer are respectively in the first connecting channel and the second connecting channel to connect the first electrode and the second electrode. The base includes an opening forming a closed cavity with the protective layer. The first electrical connection region and the second electrical connection region are respectively filled with metal materials to electrically connect the first conductive layer and the second conductive layer.Type: ApplicationFiled: September 21, 2023Publication date: January 11, 2024Inventors: Yi-Hsiang Chiu, Hung-Ping Lee
-
Patent number: 11806751Abstract: A wafer level ultrasonic device includes a composite layer, a first conductive layer, a second conductive layer, a base, a first electrical connection region, and a second electrical connection region. The composite layer includes an ultrasonic element and a protective layer. The ultrasonic element includes a first electrode and a second electrode. The protective layer has a first connecting channel and a second connecting channel respectively corresponding to the first electrode and the second electrode. The first conductive layer and the second conductive layer are respectively in the first connecting channel and the second connecting channel to connect the first electrode and the second electrode. The base includes an opening forming a closed cavity with the protective layer. The first electrical connection region and the second electrical connection region are respectively filled with metal materials to electrically connect the first conductive layer and the second conductive layer.Type: GrantFiled: May 15, 2020Date of Patent: November 7, 2023Assignee: SONICMEMS (ZHENGZHOU) TECHNOLOGY CO., LTD.Inventors: Yi-Hsiang Chiu, Hung-Ping Lee
-
Patent number: 11590536Abstract: A wafer level ultrasonic chip module includes a substrate, a composite layer, a conducting material, and a base material. The substrate has a through slot that passes through an upper surface of the substrate and a lower surface of the substrate. The composite layer includes an ultrasonic body and a protective layer. A lower surface of the ultrasonic body is exposed from the through slot. The protective layer covers the ultrasonic body and a partial upper surface of the substrate. The protective layer has an opening, from which a partial upper surface of the ultrasonic body is exposed. The conducting material is in contact with the upper surface of the ultrasonic body. The base material covers the through slot, such that a space is formed among the through slot, the lower surface of the ultrasonic body and an upper surface of the base material.Type: GrantFiled: February 13, 2019Date of Patent: February 28, 2023Assignees: PEKING UNIVERSITY SHENZHEN GRADUATE SCHOOL, SONICMEMS (ZHENGZHOU) TECHNOLOGY CO., LTD.Inventors: Yu-Feng Jin, Sheng-Lin Ma, Qian-Cheng Zhao, Yi-Hsiang Chiu, Huan Liu, Hung-Ping Lee, Dan Gong
-
Publication number: 20230014827Abstract: A wafer level ultrasonic chip module includes a substrate, a composite layer and a base material. The substrate has a through slot passing through an upper surface and a lower surface of the substrate. The composite layer includes an ultrasonic body and a protective layer. A lower surface of the ultrasonic body is exposed from the through slot. The protective layer covers the ultrasonic body and a partial upper surface of the substrate. The composite layer has a groove passing through an upper surface and a lower surface of the protective layer, and communicating with the through slot. Rhe ultrasonic body corresponds to the through slot. The base material covers the through slot, such that a space is formed among the through slot, the lower surface of the ultrasonic body and an upper surface of the base material.Type: ApplicationFiled: September 15, 2022Publication date: January 19, 2023Inventors: Yu-Feng Jin, Sheng-Lin Ma, Qian-Cheng Zhao, Yi-Hsiang Chiu, Huan Liu, Hung-Ping Lee, Dan Gong
-
Patent number: 11548031Abstract: An array-type ultrasonic sensor includes a semiconductor substrate, a first sensing array, and a second sensing array. The first sensing array includes a plurality of first ultrasonic sensing units. Each of the first ultrasonic sensing units includes a first positive electrode and a first negative electrode. The first positive electrodes are connected in series with each other, and the first negative electrodes are connected in series with each other. The second sensing array includes a plurality of second ultrasonic sensing units. Each of the second ultrasonic sensing units includes a second positive electrode and a second negative electrode. The second positive electrodes are connected in series with each other, and the second negative electrodes are connected in series with each other. One of the first sensing array and the second sensing array is configured to transmit ultrasonic waves, and the other is configured to receive reflected ultrasonic waves.Type: GrantFiled: May 28, 2021Date of Patent: January 10, 2023Assignee: SONICMEMS (ZHENGZHOU) TECHNOLOGY CO., LTD.Inventors: Yi-Hsiang Chiu, Hung-Ping Lee
-
Patent number: 11478822Abstract: A wafer level ultrasonic chip module includes a substrate, a composite layer and a base material. The substrate has a through slot passing through an upper surface and a lower surface of the substrate. The composite layer includes an ultrasonic body and a protective layer. A lower surface of the ultrasonic body is exposed from the through slot. The protective layer covers the ultrasonic body and a partial upper surface of the substrate. The composite layer has a groove passing through an upper surface and a lower surface of the protective layer, and communicating with the through slot. The ultrasonic body corresponds to the through slot. The base material covers the through slot, such that a space is formed among the through slot, the lower surface of the ultrasonic body and an upper surface of the base material.Type: GrantFiled: February 13, 2019Date of Patent: October 25, 2022Assignees: J-Metrics Technology Co., Ltd., Peking University Shenzhen Graduate SchoolInventors: Yu-Feng Jin, Sheng-Lin Ma, Qian-Cheng Zhao, Yi-Hsiang Chiu, Huan Liu, Hung-Ping Lee, Dan Gong
-
Patent number: 11460341Abstract: A wafer scale ultrasonic sensor assembly includes a wafer substrate, an ultrasonic element, first and second protective layers, conductive wires, a transmitting material, an ASIC, a conductive bump, and a soldering portion. The wafer substrate includes a via. The ultrasonic element is exposed to the via. The conductive wires are on the first protective layer and connected to the ultrasonic element. The second protective layer covers the conductive wires, and the second protective layer has an opening corresponding to the ultrasonic element. The transmitting material contacts the ultrasonic element. The ASIC is connected to the wafer substrate, so that the via forms a space between the ASIC and the ultrasonic element. The conductive pillar is in a via defined through the ASIC, the wafer substrate, and the first protective layer, and the conducive pillar is respectively connected to the conductive wires and the soldering portion.Type: GrantFiled: June 3, 2019Date of Patent: October 4, 2022Assignees: j-Metrics Technology Co., Ltd., Peking University Shenzhen Graduate SchoolInventors: Yu-Feng Jin, Sheng-Lin Ma, Yi-Hsiang Chiu, Hung-Ping Lee, Dan Gong
-
Publication number: 20220226862Abstract: An array-type ultrasonic sensor includes a semiconductor substrate, a first sensing array, and a second sensing array. The first sensing array includes a plurality of first ultrasonic sensing units. Each of the first ultrasonic sensing units includes a first positive electrode and a first negative electrode. The first positive electrodes are connected in series with each other, and the first negative electrodes are connected in series with each other. The second sensing array includes a plurality of second ultrasonic sensing units. Each of the second ultrasonic sensing units includes a second positive electrode and a second negative electrode. The second positive electrodes are connected in series with each other, and the second negative electrodes are connected in series with each other. One of the first sensing array and the second sensing array is configured to transmit ultrasonic waves, and the other is configured to receive reflected ultrasonic waves.Type: ApplicationFiled: May 28, 2021Publication date: July 21, 2022Inventors: Yi-Hsiang Chiu, Hung-Ping Lee
-
Patent number: 11075072Abstract: A wafer scale ultrasonic sensing device includes a substrate assembly, an ultrasonic component, a first protective layer, a first conductive circuit, a second conductive circuit, a second protective layer, a conductive material, electrical connection layers, and soldering portions. The substrate assembly includes a first wafer and a second wafer, and the second wafer covers a groove on the first wafer to define a hollow chamber. The first wafer, the second wafer, and the first protective layer are coplanar with the first conductive circuit on a first side surface and coplanar with the second conductive circuit on a second side surface. The second protective layer has an opening, where the conductive material is in the opening and is in contact with the ultrasonic component. The electrical connection layers are on the first side surface and the second side surface, and the soldering portions are respectively connected to the electrical connection layers.Type: GrantFiled: May 14, 2020Date of Patent: July 27, 2021Assignees: J-Metrics Technology Co., Ltd., Peking University Shenzhen Graduate SchoolInventors: Yu-Feng Jin, Sheng-Lin Ma, Qian-Cheng Zhao, Yi-Hsiang Chiu, Huan Liu, Hung-Ping Lee, Dan Gong
-
Publication number: 20210170448Abstract: A wafer level ultrasonic device includes a composite layer, a first conductive layer, a second conductive layer, a base, a first electrical connection region, and a second electrical connection region. The composite layer includes an ultrasonic element and a protective layer. The ultrasonic element includes a first electrode and a second electrode. The protective layer has a first connecting channel and a second connecting channel respectively corresponding to the first electrode and the second electrode. The first conductive layer and the second conductive layer are respectively in the first connecting channel and the second connecting channel to connect the first electrode and the second electrode. The base includes an opening forming a closed cavity with the protective layer. The first electrical connection region and the second electrical connection region are respectively filled with metal materials to electrically connect the first conductive layer and the second conductive layer.Type: ApplicationFiled: May 15, 2020Publication date: June 10, 2021Inventors: Yi-Hsiang CHIU, Hung-Ping LEE
-
Publication number: 20210013026Abstract: A wafer scale ultrasonic sensing device includes a substrate assembly, an ultrasonic component, a first protective layer, a first conductive circuit, a second conductive circuit, a second protective layer, a conductive material, electrical connection layers, and soldering portions. The substrate assembly includes a first wafer and a second wafer, and the second wafer covers a groove on the first wafer to define a hollow chamber. The first wafer, the second wafer, and the first protective layer are coplanar with the first conductive circuit on a first side surface and coplanar with the second conductive circuit on a second side surface. The second protective layer has an opening, where the conductive material is in the opening and is in contact with the ultrasonic component. The electrical connection layers are on the first side surface and the second side surface, and the soldering portions are respectively connected to the electrical connection layers.Type: ApplicationFiled: May 14, 2020Publication date: January 14, 2021Inventors: Yu-Feng JIN, Sheng-Lin MA, Qian-Cheng ZHAO, Yi-Hsiang CHIU, Huan LIU, Hung-Ping LEE, Dan GONG
-
Publication number: 20200203319Abstract: A mass transfer method for micro light emitting diode (LED) includes a micro-LED manufacturing step, a connecting step, a removing step, a fluorescent-powder layer forming step, and a filtering-sheet forming step. In the micro-LED manufacturing step, micro-LEDs are formed on a wafer substrate. Each micro-LED includes first and second electrodes. In the connecting step, the wafer substrate including the micro-LEDs is connected with a circuit substrate including first electrical-connection portions and second electrical-connection portions. Each first electrical-connection portion is connected to the first electrode of the corresponding micro-LED, and each second electrical-connection portion is connected to the second electrode of the corresponding micro-LED. In the removing step, the wafer substrate is removed. In the fluorescent-powder layer forming step, a fluorescent-powder layer is formed on the light-emitting surface of each of the micro-LEDs.Type: ApplicationFiled: July 2, 2019Publication date: June 25, 2020Inventors: Hung-Ping LEE, Yi-Hsiang CHIU
-
Publication number: 20200191646Abstract: A wafer scale ultrasonic sensor assembly includes a wafer substrate, an ultrasonic element, first and second protective layers, conductive wires, a transmitting material, an ASIC, a conductive bump, and a soldering portion. The wafer substrate includes a via. The ultrasonic element is exposed to the via. The conductive wires are on the first protective layer and connected to the ultrasonic element. The second protective layer covers the conductive wires, and the second protective layer has an opening corresponding to the ultrasonic element. The transmitting material contacts the ultrasonic element. The ASIC is connected to the wafer substrate, so that the via forms a space between the ASIC and the ultrasonic element. The conductive pillar is in a via defined through the ASIC, the wafer substrate, and the first protective layer, and the conducive pillar is respectively connected to the conductive wires and the soldering portion.Type: ApplicationFiled: June 3, 2019Publication date: June 18, 2020Inventors: Yu-Feng Jin, Sheng-Lin Ma, Yi-Hsiang Chiu, Hung-Ping Lee, Dan Gong
-
Publication number: 20200179979Abstract: A wafer level ultrasonic chip module includes a substrate, a composite layer, a conducting material, and a base material. The substrate has a through slot that passes through an upper surface of the substrate and a lower surface of the substrate. The composite layer includes an ultrasonic body and a protective layer. A lower surface of the ultrasonic body is exposed from the through slot. The protective layer covers the ultrasonic body and a partial upper surface of the substrate. The protective layer has an opening, from which a partial upper surface of the ultrasonic body is exposed. The conducting material is in contact with the upper surface of the ultrasonic body. The base material covers the through slot, such that a space is formed among the through slot, the lower surface of the ultrasonic body and an upper surface of the base material.Type: ApplicationFiled: February 13, 2019Publication date: June 11, 2020Inventors: Yu-Feng JIN, Sheng-Lin MA, Qian-Cheng ZHAO, Yi-Hsiang CHIU, Huan LIU, Hung-Ping LEE, Dan GONG
-
Publication number: 20200164406Abstract: A wafer level ultrasonic chip module includes a substrate, a composite layer and a base material. The substrate has a through slot passing through an upper surface and a lower surface of the substrate. The composite layer includes an ultrasonic body and a protective layer. A lower surface of the ultrasonic body is exposed from the through slot. The protective layer covers the ultrasonic body and a partial upper surface of the substrate. The composite layer has a groove passing through an upper surface and a lower surface of the protective layer, and communicating with the through slot. Rhe ultrasonic body corresponds to the through slot. The base material covers the through slot, such that a space is formed among the through slot, the lower surface of the ultrasonic body and an upper surface of the base material.Type: ApplicationFiled: February 13, 2019Publication date: May 28, 2020Inventors: Yu-Feng JIN, Sheng-Lin MA, Qian-Cheng ZHAO, Yi-Hsiang CHIU, Huan LIU, Hung-Ping LEE, Dan GONG
-
Patent number: 10120634Abstract: The present disclosure provides an LED display device. The LED display device divides each of LED modules into a plurality of unit blocks. In each of the unit blocks, a display controller transmits image data to be processed in parallel to the corresponding data driver at the same time, and transmits logic signals to the corresponding gate driver, thereby driving the corresponding data driver and then turning on the corresponding LEDs. Therefore, the speed processing the image data of each unit block can be improved, to enhance the visual refresh rate.Type: GrantFiled: September 29, 2016Date of Patent: November 6, 2018Assignee: ANPEC ELECTRONICS CORPORATIONInventor: Hung-Ping Lee
-
Publication number: 20180011677Abstract: The present disclosure provides an LED display device. The LED display device divides each of LED modules into a plurality of unit blocks. In each of the unit blocks, a display controller transmits image data to be processed in parallel to the corresponding data driver at the same time, and transmits logic signals to the corresponding gate driver, thereby driving the corresponding data driver and then turning on the corresponding LEDs. Therefore, the speed processing the image data of each unit block can be improved, to enhance the visual refresh rate.Type: ApplicationFiled: September 29, 2016Publication date: January 11, 2018Inventor: HUNG-PING LEE
-
Publication number: 20140048828Abstract: An LED display panel includes: a semiconductor wafer having a top surface; a plurality of LED elements disposed over the top surface of the semiconductor wafer, each of the LED elements having an electrode contact; and a plurality of driving circuits formed in the semiconductor wafer. Each of the driving circuits has an electrode-connecting contact that is disposed on the top surface of the semiconductor wafer and that is bonded to the electrode contact of a respective one of the LED elements.Type: ApplicationFiled: August 15, 2013Publication date: February 20, 2014Applicant: Macroblock Inc.Inventors: Li-Chang YANG, Chung-Yu WU, Hung-Ping LEE