Abstract: The present invention provides a computer system with random access memory at power up and a method for providing random access memory for use by the processor during initialization of the dynamic random access memory. A static random access memory unit is provided and coupled to the processor. It is assigned memory locations which overlay a portion of read only memory address space. BIOS code and selection logic provide signals to select either the read only memory or the static random access memory so that initialization code has sufficient random access memory to operate efficiently while it initializes the dynamic random access memory.

Abstract: The present invention provides a computer system with random access memory at power up and a method for providing random access memory for use by the processor during initialization of the dynamic random access memory. A static random access memory unit is provided and coupled to the processor. It is assigned memory locations which overlay a portion of read only memory address space. BIOS code and selection logic provide signals to select either the read only memory or the static random access memory so that initialization code has sufficient random access memory to operate efficiently while it initializes the dynamic random access memory.

Abstract: A computer system audio circuit is connected to a sound device, a combination game/MIDI/line-in/line-out/headphone jack, and internal loudspeaker. The circuit routes audio signals to a headphone, when the headphones are plugged into the headphone connector of the combination jack. In addition, the audio circuit switches and does not route audio signal to the internal loudspeaker nor external loudspeakers when the headphones are plugged in. Furthermore, if the external loudspeakers are plugged into the line-out connector of the combination jack, the circuit provides audio to the external loudspeakers but not the internal loudspeaker.

Abstract: A highly parallel computer system including dual processors and dual memory controllers are coupled to an Assisted Gunning Transceiver Logic Plus (AGTL+) high speed system bus. The microprocessors are designed for a quad processor architecture requiring four processors and four connectors for the processors. To maintain signal timing and integrity in a dual processor/dual memory controller architecture, additional terminations are inserted. Printed circuit board space is conserved with a dual processor architecture. The additional connectors and traces to the additional connectors for the processors are no longer needed. Furthermore, with the dual processor design, there is no need for two additional termination cards.