Patents by Inventor Hung-Sheng CHOU

Hung-Sheng CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12322686
    Abstract: A redistribution layer structure is provided. The redistribution layer structure includes a first metal layer, a first dielectric layer disposed on the first metal layer, a second metal layer disposed on the first dielectric layer, and a second dielectric layer disposed on the second metal layer. A coefficient of thermal expansion of the first dielectric layer is less than a coefficient of thermal expansion of the second dielectric layer.
    Type: Grant
    Filed: November 21, 2021
    Date of Patent: June 3, 2025
    Assignee: Innolux Corporation
    Inventors: Hung-Sheng Chou, Wen-Hsiang Liao, Kuo-Jung Fan, Heng-Shen Yeh, Cheng-Chi Wang
  • Publication number: 20250038089
    Abstract: An electronic device includes a first metal layer, a first insulating layer disposed on the first metal layer, a second metal layer, a second insulating layer, a third metal layer, a third insulating layer, a fourth metal layer, a fourth insulating layer and an electronic component. The second metal layer is disposed on the first insulating layer. The second insulating layer is disposed on the second metal layer. The third metal layer is disposed on the second insulating layer. The third insulating layer is disposed on the third metal layer. The fourth metal layer is disposed on the third insulating layer. The fourth insulating layer is disposed on the fourth metal layer. The electronic component is disposed on the fourth insulating layer and electrically connected to the fourth metal layer. A Young's modulus of the third insulating layer is less than a Young's modulus of the first insulating layer.
    Type: Application
    Filed: October 13, 2024
    Publication date: January 30, 2025
    Applicant: Innolux Corporation
    Inventors: Hung-Sheng Chou, Wen-Hsiang Liao, Kuo-Jung Fan, Heng-Shen Yeh, Cheng-Chi Wang
  • Patent number: 12148685
    Abstract: A redistribution layer structure is provided. The redistribution layer structure includes a first metal layer and a first dielectric layer disposed on the first metal layer. A range of a difference between a coefficient of thermal expansion of the first dielectric layer and a coefficient of thermal expansion of the first metal layer is 0% to 70% of the coefficient of thermal expansion of the first dielectric layer.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: November 19, 2024
    Assignee: Innolux Corporation
    Inventors: Hung-Sheng Chou, Wen-Hsiang Liao, Kuo-Jung Fan, Heng-Shen Yeh, Cheng-Chi Wang
  • Patent number: 11769685
    Abstract: A manufacturing method of a semiconductor package is provided. The manufacturing method includes the following. A plurality of semiconductor components are provided. Each semiconductor component has at least one conductive bump. A substrate is provided. The substrate has a plurality of conductive pads. A transfer device is provided. The transfer device transfers the semiconductor components onto the substrate. A heating device is provided. The heating device heats or pressurizes at least two semiconductor components. During transferring of the semiconductor components to the substrate, the at least one conductive bump of each semiconductor component is docked to a corresponding one of the conductive pads.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: September 26, 2023
    Assignee: Innolux Corporation
    Inventors: Cheng-Chi Wang, Wen-Hsiang Liao, Yeong-E Chen, Hung-Sheng Chou, Cheng-En Cheng
  • Publication number: 20220189862
    Abstract: A redistribution layer structure is provided. The redistribution layer structure includes a first metal layer and a first dielectric layer disposed on the first metal layer. A range of a difference between a coefficient of thermal expansion of the first dielectric layer and a coefficient of thermal expansion of the first metal layer is 0% to 70% of the coefficient of thermal expansion of the first dielectric layer.
    Type: Application
    Filed: November 18, 2021
    Publication date: June 16, 2022
    Applicant: Innolux Corporation
    Inventors: Hung-Sheng Chou, Wen-Hsiang Liao, Kuo-Jung Fan, Heng-Shen Yeh, Cheng-Chi Wang
  • Publication number: 20220189863
    Abstract: A redistribution layer structure is provided. The redistribution layer structure includes a first metal layer, a first dielectric layer disposed on the first metal layer, a second metal layer disposed on the first dielectric layer, and a second dielectric layer disposed on the second metal layer. A coefficient of thermal expansion of the first dielectric layer is less than a coefficient of thermal expansion of the second dielectric layer.
    Type: Application
    Filed: November 21, 2021
    Publication date: June 16, 2022
    Applicant: Innolux Corporation
    Inventors: Hung-Sheng Chou, Wen-Hsiang Liao, Kuo-Jung Fan, Heng-Shen Yeh, Cheng-Chi Wang
  • Publication number: 20220181189
    Abstract: A manufacturing method of a semiconductor package is provided. The manufacturing method includes the following. A plurality of semiconductor components are provided. Each semiconductor component has at least one conductive bump. A substrate is provided. The substrate has a plurality of conductive pads. A transfer device is provided. The transfer device transfers the semiconductor components onto the substrate. A heating device is provided. The heating device heats or pressurizes at least two semiconductor components. During transferring of the semiconductor components to the substrate, the at least one conductive bump of each semiconductor component is docked to a corresponding one of the conductive pads.
    Type: Application
    Filed: November 5, 2021
    Publication date: June 9, 2022
    Applicant: Innolux Corporation
    Inventors: Cheng-Chi Wang, Wen-Hsiang Liao, Yeong-E Chen, Hung-Sheng Chou, Cheng-En Cheng
  • Publication number: 20180312995
    Abstract: The present disclosure provides a polycrystalline silicon ingot. The polycrystalline silicon ingot has a vertical direction and includes a nucleation promotion layer located at a bottom of the polycrystalline silicon ingot, and silicon grains grown along the vertical direction, wherein the silicon grains include at least three crystal directions. The coefficient of variation of grain area in a section above the nucleation promotion layer of the polycrystalline silicon ingot increases along the vertical direction.
    Type: Application
    Filed: July 2, 2018
    Publication date: November 1, 2018
    Applicant: Sino-American Silicon Products Inc.
    Inventors: Yu-Min Yang, Cheng-Jui Yang, Hung-Sheng Chou, Wen-Huai Yu, Sung-Lin Hsu, Wen-Ching Hsu
  • Publication number: 20180297851
    Abstract: Present disclosure provides a multicrystalline silicon (mc-Si) brick, including a bottom portion starting from a bottom to a height of 100 mm, a middle portion starting from the height of 100 mm to a height of 200 mm; and a top portion starting from the height of 200 mm to a top. A percentage of incoherent grain boundary in the bottom portion is greater than a percentage of incoherent grain boundary in the top portion. Present disclosure also provides a multicrystalline silicon (mc-Si) wafer. The mc-Si wafer includes a percentage of non-? grain boundary from about 60 to about 75 and a percentage of ?3 grain boundary from about 12 to about 25.
    Type: Application
    Filed: June 22, 2018
    Publication date: October 18, 2018
    Inventors: Hung-Sheng CHOU, Yu-Min YANG, Wen-Huai YU, Sung Lin HSU, Wen-Ching HSU, Chung-Wen LAN, Yu-Ting WONG
  • Patent number: 10029919
    Abstract: Present disclosure provides a multicrystalline silicon (mc-Si) brick, including a bottom portion starting from a bottom to a height of 100 mm, a middle portion starting from the height of 100 mm to a height of 200 mm; and a top portion starting from the height of 200 mm to a top. A percentage of incoherent grain boundary in the bottom portion is greater than a percentage of incoherent grain boundary in the top portion. Present disclosure also provides a multicrystalline silicon (mc-Si) wafer. The mc-Si wafer includes a percentage of non-? grain boundary from about 60 to about 75 and a percentage of ?3 grain boundary from about 12 to about 25.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: July 24, 2018
    Assignee: SINO-AMERICAN SILICON PRODUCTS INC.
    Inventors: Hung-Sheng Chou, Yu-Min Yang, Wen-Huai Yu, Sung Lin Hsu, Wen-Ching Hsu, Chung-Wen Lan, Yu-Ting Wong
  • Patent number: 9903043
    Abstract: The invention provides a crucible assembly and method of manufacturing a crystalline silicon ingot by use of such crucible assembly. The crucible assembly of the invention includes a crucible body and a fiber textile article. The fiber textile article is made of a plurality of carbon fibers, and is loaded on a bottom of the crucible body. The fiber textile article has a plurality of intrinsic pores randomly arranged.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: February 27, 2018
    Assignee: SINO-AMERICAN SULICON PRODUCTS INC.
    Inventors: Wen-Huai Yu, Hung-Sheng Chou, Yu-Min Yang, Kuo-Wei Chuang, Sung-Lin Hsu, I-Ching Li, Wen-Ching Hsu
  • Patent number: 9885125
    Abstract: A method for manufacturing an isolating layer onto a crucible includes the steps as follows: providing a spraying device for the following spraying steps; heating the crucible and measuring the heated crucible to get a first temperature; spraying a slurry on the inner wall of the crucible to form an isolating layer by a spraying unit with a predetermined spraying manner; measuring the isolating layer to get a second temperature; obtaining a value for the difference between the first and second temperatures and judging whether the difference value in a within predetermined difference scope or not, in which the predetermined difference scope is about 6° C.˜12° C.; when the difference value is not in the predetermined difference scope, adjusting the predetermined spraying manner; when the difference value is in the predetermined difference scope, implementing the above spraying steps to the crucible.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: February 6, 2018
    Assignee: Sino-American Silicon Products Inc.
    Inventors: Hung-Sheng Chou, Li Wei Li, Wen-Huai Yu, Bruce Hsu, Chun-I Fan, Wen Ching Hsu
  • Publication number: 20170016143
    Abstract: The present disclosure provides a polycrystalline silicon ingot, a polycrystalline silicon brick and a polycrystalline silicon wafer. The polycrystalline silicon ingot has a vertical direction and includes a nucleation promotion layer located at a bottom of the polycrystalline silicon ingot, and a plurality of silicon grains grown along the vertical direction, wherein the silicon grains include at least three crystal directions. The coefficient of variation of grain area in a section above the nucleation promotion layer of the polycrystalline silicon ingot increases along the vertical direction.
    Type: Application
    Filed: May 13, 2016
    Publication date: January 19, 2017
    Inventors: Yu-Min Yang, Cheng-Jui Yang, Hung-Sheng Chou, Wen-Huai Yu, Sung-Lin Hsu, Wen-Ching Hsu
  • Patent number: 9337375
    Abstract: The invention discloses a seed used for crystalline silicon ingot casting. A seed according to a preferred embodiment of the invention includes a crystal and an impurity diffusion-resistant layer. The crystal is constituted by at least one grain. The impurity diffusion-resistant layer is formed to overlay an outer surface of the crystal. A crystalline silicon ingot fabricated by use of the seed of the invention has significantly reduced red zone and yellow zone.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 10, 2016
    Assignee: Sino-American Silicon Products Inc.
    Inventors: Hung-Sheng Chou, Yu-Tsung Chiang, Yu-Min Yang, Ming-Kung Hsiao, Wen-Huai Yu, Sung-Lin Hsu, I-Ching Li, Chung-Wen Lan, Wen-Ching Hsu
  • Publication number: 20150361577
    Abstract: A method of casting an ingot includes the following steps: place solid silicon raw materials on a bottom of a containing device, wherein the containing device includes a container and a graphite layer provided on a surrounding wall and an inner bottom of the container, and the solid silicon raw materials are stacked upon the graphite layer on the inner bottom; heat the container to melt the solid silicon raw material into liquid state; cool the container from the bottom up till all of the silicon raw materials are crystallized and solidified. The solidified silicon raw materials become an ingot. Whereby, the graphite layer can effectively prevent impurities of the container from contaminating the ingot.
    Type: Application
    Filed: June 8, 2015
    Publication date: December 17, 2015
    Inventors: Hung-Sheng CHOU, Kuo-Wei Chuang, Yu-Min Yang, Wen-Huai Yu, Sung-Lin Hsu, Wen-Ching Hsu
  • Publication number: 20150307361
    Abstract: Present disclosure provides a multicrystalline silicon (mc-Si) brick, including a bottom portion starting from a bottom to a height of 100 mm, a middle portion starting from the height of 100 mm to a height of 200 mm; and a top portion starting from the height of 200 mm to a top. A percentage of incoherent grain boundary in the bottom portion is greater than a percentage of incoherent grain boundary in the top portion. Present disclosure also provides a multicrystalline silicon (mc-Si) wafer. The mc-Si wafer includes a percentage of non-? grain boundary from about 60 to about 75 and a percentage of ?3 grain boundary from about 12 to about 25.
    Type: Application
    Filed: April 28, 2015
    Publication date: October 29, 2015
    Inventors: Hung-Sheng CHOU, Yu-Min YANG, Wen-Huai YU, Sung Lin HSU, Wen-Ching HSU, Chung-Wen LAN, Yu-Ting WONG
  • Publication number: 20150259820
    Abstract: A method for manufacturing an isolating layer onto a crucible includes the steps as follows: providing a spraying device for the following spraying steps; heating the crucible and measuring the heated crucible to get a first temperature; spraying a slurry on the inner wall of the crucible to form an isolating layer by a spraying unit with a predetermined spraying manner; measuring the isolating layer to get a second temperature; obtaining a value for the difference between the first and second temperatures and judging whether the difference value in a within predetermined difference scope or not, in which the predetermined difference scope is about 6° C.˜12° C.; when the difference value is not in the predetermined difference scope, adjusting the predetermined spraying manner; when the difference value is in the predetermined difference scope, implementing the above spraying steps to the crucible.
    Type: Application
    Filed: March 12, 2015
    Publication date: September 17, 2015
    Inventors: HUNG-SHENG CHOU, LI WEI LI, WEN-HUAI YU, BRUCE HSU, CHUN-I FAN, WEN CHING HSU
  • Publication number: 20150197873
    Abstract: The invention provides a crucible assembly and method of manufacturing a crystalline silicon ingot by use of such crucible assembly. The crucible assembly of the invention includes a crucible body and a fiber textile article. The fiber textile article is made of a plurality of carbon fibers, and is loaded on a bottom of the crucible body. The fiber textile article has a plurality of intrinsic pores randomly arranged.
    Type: Application
    Filed: January 16, 2015
    Publication date: July 16, 2015
    Inventors: Wen-Huai YU, Hung-Sheng CHOU, Yu-Min YANG, Kuo-Wei CHUANG, Sung-Lin HSU, I-Ching LI, Wen-Ching HSU
  • Publication number: 20140186631
    Abstract: The invention discloses a seed used for crystalline silicon ingot casting. A seed according to a preferred embodiment of the invention includes a crystal and an impurity diffusion-resistant layer. The crystal is constituted by at least one grain. The impurity diffusion-resistant layer is formed to overlay an outer surface of the crystal. A crystalline silicon ingot fabricated by use of the seed of the invention has significantly reduced red zone and yellow zone.
    Type: Application
    Filed: December 23, 2013
    Publication date: July 3, 2014
    Applicant: Sino-American Silicon Products Inc.
    Inventors: Hung-Sheng CHOU, Yu-Tsung CHIANG, Yu-Min YANG, Ming-Kung HSIAO, Wen-Huai YU, Sung-Lin HSU, I-Ching LI, Chung-Wen LAN, Wen-Ching HSU