Abstract: A semiconductor structure includes a first, second and third isolations. The first isolation and a second isolation are disposed in a substrate and substantially parallel to each other, wherein a portion of the substrate is disposed between the first isolation and the second isolations. The third isolation is disposed over the portion of the substrate between the first and second isolations. A top surface of the third isolation is substantially aligned with top surfaces of the first and second isolations. A first step is between a bottom surface of the third isolation and a bottom surface of the first isolation. A second step between the bottom surface of the third isolation and a bottom surface of the second isolation. A method for manufacturing a semiconductor structure is also provided.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Abstract: A data processing device includes a base plate and an electronic module. The base plate includes N driving portions. The electronic module includes an electronic component, a tray and a recognition mechanism. The tray is configured to support the electronic component and includes N slots. The tray is disposed on the base plate, such that an i-th driving portion of the N driving portions is disposed in an i-th slot of the N slots. The recognition mechanism is disposed on the tray. The recognition mechanism includes N interfering portions and N receiving recesses. When the tray moves with respect to the base plate toward a first direction, the i-th driving portion moves within the i-th slot toward a second direction to push an i-th interfering portion of the N interfering portions to move, such that the i-th interfering portion extends into an i-th receiving recess of the N receiving recesses.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: The present invention relates to an authentication information manager computer program product, which is executed by a processing unit. The computer program product includes: a physical private key acquisition module configured to receive an identity information to form an initialization authentication information including a part of the identity information; an authentication information management module configured to record a first set of authentication information for logging into a first networking application; and a multiparty multifactor dynamic strong encryption authentication transmission module configured to implement a multiparty multifactor dynamic digital authentication method with strong encryption to transmit the transfigurated initialization authentication information to a network application serving device including an authentication information manager back end and a third-party security serving equipment to be verified.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: The invention provides an optical coherence tomography self-testing system, an optical coherence tomography method and an ocular disease monitoring system. The optical coherence tomography self-testing system comprises a camera device, an external display module and a communication module. The camera device includes an image-capturing module and a processing module. The image-capturing module captures a plurality of ocular images. The processing module is connected to the image-capturing module, and the processing module determines whether a position offset value between the pupil center position of a tested eyeball and an optical axis of the image-capturing module is within a preset error range. If the position offset value is within the preset error range, the plurality of ocular images is stored as a plurality of displayed images. The external display module displays one of the plurality of displayed images and a status light after the image-capturing module has completed image capturing.

Abstract: A device with lock function includes a housing, a casing and a lock mechanism. The housing has a first engaging portion. The lock mechanism includes a frame, a lock member, a first elastic member, an operating member and an unlock member. The frame has a second engaging portion. The lock member has a third engaging portion engaging with the first engaging portion to lock the casing in the housing. The unlock member has a fourth engaging portion engaging with the second engaging portion to restrain the operating member. When the unlock member is pressed, the fourth engaging portion disengages from the second engaging portion and the first elastic member drives the lock member to move toward an inside of the frame, such that the third engaging portion disengages from the first engaging portion and the lock member drives the operating member to move toward an outside of the frame.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a doped semiconductor layer, and a dielectric structure. The semiconductor fin has a top portion and a lower portion extending from the top portion to a substrate. The gate structure extends across the semiconductor fin. The doped semiconductor layer interfaces the top portion of the semiconductor fin. In a cross-section taken along a lengthwise direction of the gate structure, the doped semiconductor layer has an outer profile conformal to a profile of the top portion of the semiconductor fin.

Abstract: A light guide plate is adapted for a backlight module having at least one light emitting device, and the light guide plate includes a light emitting surface, a surface opposite to the light emitting surface, a light incident surface connected with the light emitting surface and the surface, and a plurality of microstructures disposed on the light emitting surface or the surface. 90 percent or more of the surface or the light emitting surface is flat. At least one of the light emitting devices is disposed beside the light incident surface and capable of emitting a light beam. The light incident surface is capable of making the light beam enter the light guide plate and the light emitting surface is capable of making the light beam transmit outside the light guide plate. A backlight module is also provided.

Abstract: A light guide plate is adapted for a backlight module having at least one light emitting device, and the light guide plate includes a light emitting surface, a surface opposite to the light emitting surface, a light incident surface connected with the light emitting surface and the surface, and a plurality of microstructures disposed on the light emitting surface or the surface. 90 percent or more of the surface or the light emitting surface is flat. At least one of the light emitting devices is disposed beside the light incident surface and capable of emitting a light beam. The light incident surface is capable of making the light beam enter the light guide plate and the light emitting surface is capable of making the light beam transmit outside the light guide plate. A backlight module is also provided.