Abstract: The present invention discloses a multipurpose half bridge signal output circuit. The multipurpose half bridge signal output circuit is capable of selectively operating under a charge sharing mode or a gate pulsing modulation mode. The multipurpose half bridge signal output circuit includes: a first output pin; a second output pin; a first circuit zone having a first common end coupled to the first output pin; and a second circuit zone having a second common end coupled to the second output pin.

Abstract: The present invention discloses a multipurpose half bridge signal output circuit. The multipurpose half bridge signal output circuit is capable of selectively operating under a charge sharing mode or a gate pulsing modulation mode. The multipurpose half bridge signal output circuit includes: a first output pin; a second output pin; a first circuit zone having a first common end coupled to the first output pin; and a second circuit zone having a second common end coupled to the second output pin.

Abstract: For a charge pump, a control circuit switches two or more input voltages to apply to one or more pumping capacitors under auto-sensing control to modulate a maximum pumping voltage as close as to a demanded output voltage to thereby reduce the difference between the maximum pumping voltage and the output voltage for efficiency and thermal improvement of the charge pump. The maximum pumping voltage is produced by mixing the different input voltages and the charge pump may provide more operation modes.

Abstract: For a charge pump, a control circuit switches two or more input voltages to apply to one or more pumping capacitors under auto-sensing control to modulate a maximum pumping voltage as close as to a demanded output voltage to thereby reduce the difference between the maximum pumping voltage and the output voltage for efficiency and thermal improvement of the charge pump. The maximum pumping voltage is produced by mixing the different input voltages and the charge pump may provide more operation modes.

Abstract: A negative voltage detection circuit for a synchronous rectifier metal oxide silicon field effect transistor (MOSFET). The circuit comprises a reference current source, a first circuit mirroring a first current based upon the reference current source and generating a first voltage based upon a detection voltage, a second circuit mirroring a second current based upon the reference current source and generating a second voltage, and a comparator having input ends to receive the first voltage and the second voltage, wherein a level of an output voltage of the comparator changes when the detection voltage is equivalent to a value predetermined according to a difference between the first current and the second current.

Abstract: A circuit for predicting the dead time is provided. The circuit comprises a plurality of integrators, a plurality of comparators, and a logic circuit. Based on a reference signal provided externally, a first charging operation is delayed by a predetermined delay time during one period of the reference signal, such that the integrators maintain at a voltage level in a next period of the reference signal. Then, the integrators further perform another charging operation during the next period, and the charging voltage is compared with the maintained voltage value. When the charging voltage exceeds the maintained voltage, a reset signal is generated by the logic circuit.

Abstract: A circuit for predicting the dead time is provided. The circuit includes a plurality of integrators, a plurality of comparators, and a logic circuit. Based on a reference signal provided externally, a first charging operation is delayed by a predetermined delay time during one period of the reference signal, such that the integrators maintain at a voltage level in a next period of the reference signal. Then, the integrators further perform another charging operation during the next period, and the charging voltage is compared with the maintained voltage value. When the charging voltage exceeds the maintained voltage, a reset signal is generated by the logic circuit.