Abstract: A sectional-type raised garden bed structure includes a first wall section being provided at an end with at least one mortise, a second wall section being provided at an end with at least one tenon adapted to engage with the at least one mortise on the first wall section for connecting the first and the second wall section together. The tenon is flexible for the connected first and second wall sections to contain a predetermined angle therebetween according to actual need.

Abstract: A core logic circuit which works with a CPU and a main graphics accelerator in a computer system is provided. The core logic chip includes a host controller electrically connected to the CPU for receiving a command from the CPU; an auxiliary graphing engine electrically connected to the host controller for receiving and processing the command; and a transmission controller electrically connected to the auxiliary graphing engine for transmitting the command that is processed and outputted by the auxiliary graphing engine to the main graphics accelerator to be further processed.

Abstract: A TV decoder. The decoder comprises a converter producing a plurality of first bits by sampling a base-band TV signal within a sampling period, and transmitting the first bits in groups, wherein the first bits in each one of the groups undergo parallel transmission through a plurality of first signals, and a demodulator receives the first bits and produces a plurality of second bits controlling the first signals, wherein the second bits are sequentially transmitted through a second signal input to the converter.

Abstract: A method is adapted for compressing an image data block, and includes the steps of: (a) subjecting the image data block to discrete cosine transformation so as to generate discrete cosine transform data; (b) quantizing the discrete cosine transform data in accordance with a quantizer matrix that consists of an array of quantizing coefficients so as to generate quantized data; (c) encoding the quantized data using an entropy coding algorithm so as to generate an encoded bitstream; and (d) when the length of the encoded bitstream does not fall within a predetermined range, adjusting the quantizing coefficients in the quantizer matrix and repeating steps (b) and (c) until the length of the encoded bitstream falls within the predetermined range.

Abstract: In a method for adaptive arbitration of requests for accessing a memory unit in a multi-stage pipeline engine that includes a plurality of request queues corresponding to the stages of the pipeline engine, each of the request queues is assigned to one of a high-priority group and a low-priority group in accordance with an operating state of the memory unit. The request queues in the high-priority group are then processed prior to the request queues in the low-priority group.

Abstract: A signal transmission device adapted to transmit an n-bit parallel digital signal is used for avoiding a transmission error. The device includes a detector for receiving a first and a second n-bit digital data consecutively occurred in the n-bit parallel digital signal, proceeding a first calculation to obtain a changed value, and outputting an indicating signal while the changed value is larger than a threshold, an encoder electrically connected to the detector for receiving the indicating signal and the second n-bit digital data, proceeding a second calculation, and outputting an encoded second n-bit digital data to reduce the changed value between the first n-bit digital data and the encoded second n-bit digital data below the threshold, and a decoder electrically connected to the detector and the encoder receiving the indicating signal and the encoded second n-bit digital data, proceeding a third calculation, and recovering the second n-bit digital data.

Abstract: An apparatus automatically determines an operating frequency of an integrated circuit (IC) chip that has a built-in self-test (BIST) unit to test the chip. The apparatus includes a clock generator and a frequency determination unit. The clock generator provides a test clock to the IC chip. The frequency determination unit sets the clock generator to generate the test clock and determines the operating frequency in accordance with a test result produced from the BIST unit. The frequency determination unit also enables the BIST unit to test the IC chip. Specifically, the frequency determination unit tunes a frequency value based on the test result, and sets the clock generator to generate the test clock corresponding to the tuned frequency value. Accordingly, the apparatus determines the highest frequency passing the built-in self-test, and sets the highest frequency for the IC chip as its operating frequency.

Abstract: A TV decoder. The decoder comprises a converter producing a plurality of first bits by sampling a base-band TV signal within a sampling period, and transmitting the first bits in groups, wherein the first bits in each one of the groups undergo parallel transmission through a plurality of first signals, and a demodulator receives the first bits and produces a plurality of second bits controlling the first signals, wherein the second bits are sequentially transmitted through a second signal input to the converter.

Abstract: The present invention discloses an apparatus and method for cache memory connection of texture mapping, applied in a computer graphic processing system by storing image texels in cache memories. The apparatus comprises a plurality of cache memories. An array of image texels are stored in a plurality of cache memories to reduce the area occupied by cache memories of the computer graphic processing system. Besides, the apparatus and method of the present invention can be applied in the well-known mapping methods: selecting the nearest point, bilinear filtering and trilinear filtering. A plurality of multiplexers are used to reorganize the plurality of cache memories so as to increase the utilization efficiency of the apparatus of the present invention.

Abstract: A method and a computer system are provided for using a portion of a local memory of a graphics card as an extensive memory of a system memory. When the computer system is rebooted, a portion of a local memory of a graphics card is claimed as an extensive memory of the system memory, and the local memory excluding the extensive memory is claimed a new local memory by a driver of the graphics card. The driver of the graphics card reports the new local memory capacity to an operating system of the computer. Then, a new system memory capacity including the extensive memory and the original system memory is claimed by a chipset of the computer system and reported to a memory sizing command of BIOS. Finally, if a memory access request is within the address range of the extensive memory, the memory access request is transmitted to the graphics card through AGP/PCI bus.

Abstract: An apparatus automatically determines an operating frequency of an integrated circuit (IC) chip that has a built-in self-test (BIST) unit to test the chip. The apparatus includes a clock generator and a frequency determination unit. The clock generator provides a test clock to the IC chip. The frequency determination unit sets the clock generator to generate the test clock and determines the operating frequency in accordance with a test result produced from the BIST unit. The frequency determination unit also enables the BIST unit to test the IC chip. Specifically, the frequency determination unit tunes a frequency value based on the test result, and sets the clock generator to generate the test clock corresponding to the tuned frequency value. Accordingly, the apparatus determines the highest frequency passing the built-in self-test, and sets the highest frequency for the IC chip as its operating frequency.

Abstract: In a method for adaptive arbitration of requests for accessing a memory unit in a multi-stage pipeline engine that includes a plurality of request queues corresponding to the stages of the pipeline engine, each of the request queues is assigned to one of a high-priority group and a low-priority group in accordance with operating state of the memory unit. The request queues in the high-priority group are then processed prior to the request queues in the low-priority group.

Abstract: A core logic circuit for use with a CPU and a main graphics accelerator in a computer system is provided. The core logic chip includes a host controller electrically connected to the CPU for receiving a command from the CPU; an auxiliary graphing engine electrically connected to the host controller fore receiving and processing the command; and a transmission controller electrically connected to the auxiliary graphing engine for transmitting the command processed and outputted by the auxiliary graphing engine to the main graphics accelerator to be further processed.

Abstract: A method is adapted for compressing an image data block, and includes the steps of:

Abstract: The present invention provides a circuit for adjusting operating frequency of a chip, and comprises an oscillator, a controlling circuit, and a voltage adjusting circuit. The oscillator is coupled to the chip for outputting a testing clock signal according to a voltage signal. The controlling circuit is coupled to the oscillator for comparing the testing clock signal and a predetermined clock frequency, then outputting a voltage controlling signal. The voltage adjusting circuit is coupled to the controlling circuit for adjusting the voltage value of the voltage signal according to the voltage controlling signal.

Abstract: A signal transmission device adapted to transmit an n-bit parallel digital signal is used for avoiding a transmission error. The device includes a detector for receiving a first and a second n-bit digital data consecutively occurred in the n-bit parallel digital signal, proceeding a first calculation to obtain a changed value, and outputting an indicating signal while the changed value is larger than a threshold, an encoder electrically connected to the detector for receiving the indicating signal and the second n-bit digital data, proceeding a second calculation, and outputting an encoded second n-bit digital data to reduce the changed value between the first n-bit digital data and the encoded second n-bit digital data below the threshold, and a decoder electrically connected to the detector and the encoder receiving the indicating signal and the encoded second n-bit digital data, proceeding a third calculation, and recovering the second n-bit digital data.

Abstract: A triangle shading method for a 3D graphic system includes the steps of (1) defining a starting position and two adjacent edges; (2) setting the tile containing the starting position as a target tile, then defining a target tile row; (3) checking if the lower boundary or upper boundary of the target tile crosses with the adjacent edges and pushing the address of crossing points into a stack if there exists such crossing points; (4) storing the associated data of the pixels of the target tile in memory; (5) checking if the target tile is the final tile of the target tile row, if not, setting the target tile to be the next tile of the current target tile and jumping to step (4); (6) checking if there are data remaining in the stack, if not, jumping to step (8); (7) popping a data from the stack, setting the data as a starting position and then jumping to step (2); (8) end.

Abstract: A digital clock throttling device, for gating a clock signal of a circuit, at least includes an accumulator and a gating circuit. The accumulator responsive to a throttling value generates a first output signal. The first output signal is divided into a throttling signal with a most significant bit and a feedback signal with rest bits of the first output signal except for the most significant bit. The feedback signal is sent to the accumulator back for accumulating to the throttling value as the first output signal. The gating circuit coupling with the accumulator responsive to the throttling signal and clock signal gates out some clock cycles of the clock signal, thereby providing a gated clock signal in an adjusted frequency.

Abstract: An apparatus of reducing power consumption of a single-ended Static Random Access Memory (hereinafter referred as SRAM) is provided. The apparatus consists of at least an extra column of status memory cell and a majority detector by which a bit status of a written data is detected and by which the value of the bit status is written into the extra column of status memory cell. The apparatus further includes a data scrambler by which the written data is converted into a storage data with a minority of 0 bits based on the value of bit status and by which the storage data is written into the main single-ended SRAM cell. The apparatus further includes a data de-scrambler by which the storage data in the main single-ended SRAM cell is converted into its original format based on the value of bit status stored in the extra column of memory cell and by which the data in its original format is output.