Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: An insulated gate bipolar transistor (IGBT) includes: a semiconductor substrate having a top surface and a bottom surface extending in horizontal directions; an isolation region comprising a first silicon compound; a high thermal conductivity region comprising a second silicon compound and having a bottom portion and a sidewall portion, wherein the second silicon compound has a thermal conductivity higher than silicon; a collector region of a first conductive type disposed on the isolation region; a buffer region of a second conductive type opposite to the first conductive type disposed on the collector region; a drift region of the second conductive type disposed on the buffer region; a body region of the first conductive type disposed in the drift region; and at least one source region of the second conductive type disposed in the body region. The isolation region encircles the high thermal conductivity region in the horizontal directions.

Abstract: An insulated gate bipolar transistor (IGBT) includes: a semiconductor substrate having a top surface extending in a horizontal plane; a three-dimensional (3D) isolation region comprising a silicon compound, the 3D isolation region having a bottom portion and a sidewall portion; a collector region of a first conductive type disposed on the 3D isolation region; a buffer region of a second conductive type opposite to the first conductive type disposed on the collector region; a drift region of the second conductive type disposed on the buffer region; a body region of the first conductive type disposed in the drift region; and at least one source region of the second conductive type disposed in the body region. The 3D isolation region and the top surface of the semiconductor substrate enclose the collector region, the buffer region, the drift region, the body region, and the at least one source region.

Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

Abstract: A semiconductor arrangement and method of manufacture is provided. In some embodiments, a semiconductor arrangement includes a collector region having a first surface coplanar with a first surface of a semiconductor layer, a drift region over a portion of the collector region and having a first surface coplanar with the first surface of the semiconductor layer, and a body region over the drift region. A body contact is in the body region. An emitter contact contacts the body contact and the body region. A collector contact contacts the first surface of the collector region. A first gate structure is adjacent the first surface of the drift region, the body region, and the body contact.

Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

Abstract: One embodiment includes method for determining whether a player application is authorized to play protected content. The method comprises reading a digital signature associated with the player application from a predetermined memory location using a protection interface associated with the player application, where the digital signature comprises one or more file designations. The embodiment further comprises mapping, by the protection interface, the one or more file designations to one or more files associated with the player application and transmitting mapping information from the protection interface to a verification application stored on a storage medium. The verification application is configured to determine whether the player application is authorized to play the protected content if the one or more file designations match the one or more files based on the mapping information.

Abstract: Systems and methods for performing secure playback of media content are described. One embodiment, among others, is a method for performing secure playback of video in a hardware protection module. The method comprises receiving media content from a media player comprising video data, audio data, and navigation data. The method further comprises receiving digital rights management (DRM) information relating to the media content, removing a portion of the video data from the media content, forwarding the audio data, navigation data, and a remaining portion of the video data to the media player for decoding, and decoding, in the hardware protection module, the portion of the video data.

Abstract: A manufacturing method of an anti punch-through leakage current MOS transistor is provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate.

Abstract: A manufacturing method of an anti punch-through leakage current MOS transistor is provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate.

Abstract: An anti punch-through leakage current MOS transistor and a manufacturing method thereof are provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate.

Abstract: A system and method is disclosed for enforcing a third-party factory test during a quality verification of a newly-manufactured computing device. During an assembly line quality verification, a factory implemented test and a required third-party factory test are executed on a computing device, and then the execution verified by an external process. On verifying the required third-party factory test was executed, the computing device is configured to execute a release image on a subsequent startup of the computing device.

Abstract: An anti punch-through leakage current MOS transistor and a manufacturing method thereof are provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate.

Abstract: Systems and methods for performing secure playback of media content are described. One embodiment, among others, is a method for performing secure playback of video in a hardware protection module. The method comprises receiving media content from a media player comprising video data, audio data, and navigation data. The method further comprises receiving digital rights management (DRM) information relating to the media content, removing a portion of the video data from the media content, forwarding the audio data, navigation data, and a remaining portion of the video data to the media player for decoding, and decoding, in the hardware protection module, the portion of the video data.

Abstract: One embodiment includes method for determining whether a player application is authorized to play protected content. The method comprises reading a digital signature associated with the player application from a predetermined memory location using a protection interface associated with the player application, where the digital signature comprises one or more file designations. The embodiment further comprises mapping, by the protection interface, the one or more file designations to one or more files associated with the player application and transmitting mapping information from the protection interface to a verification application stored on a storage medium. The verification application is configured to determine whether the player application is authorized to play the protected content if the one or more file designations match the one or more files based on the mapping information.

Abstract: Systems and methods for storing and accessing encrypted content are described. At least one embodiment includes a system for storing and accessing encrypted content comprising a secure hardware device coupled to a memory comprising a trusted module, wherein the hardware device is configured to receive content from a remote location, and wherein the hardware device is configured to encrypt content and generate a key for decrypting the content. The system further comprises logic stored within the memory configured to access the encrypted content, wherein the logic comprises a plurality of decryption modules and at least one decoder.

Abstract: A method for activating video-audio data in an optical disc includes determining whether a first activation signal is received or not, a program in the optical disc allowing access to partially-featured contents of the video-audio data when the first activation signal is not received, and the program in the optical disc allowing access to fully-featured contents of the video-audio data when the first activation signal is received.

Abstract: The present invention disclosed a multiple display method. A media data is received and a first program corresponding to the media data is displayed on a first frame of a display device. The media data is analyzed to generate a second program according to a predetermined event. The second program is displayed on a second frame of the display device while displaying the first program on the first frame on a real time basis.

Abstract: The invention relates to an improved structure of a thermopile sensor, which is to employ a membrane to cover a substrate that has a cavity. Besides, a plurality of thermoelectric elements is formed on the membrane extending outwards from the central side of the membrane and is composed of two different materials connected in series. The material of the element can be a composite of metal material and semiconductor material, and an insulation layer partitions the two materials; therefore, the two materials are connected in series through a contact hole. In addition, the contact hole formed at the central side of the membrane is called hot junction, whereas the contact hole formed at the side of the substrate is called cold junction. Moreover, to enhance the sensing performance of the thermopile sensor, a heat-conducting layer is formed at the center of the membrane, and after the heat-conducting layer is covered with another insulation layer, an absorption film is formed.