Abstract: A semiconductor interconnect structure including a semiconductor substrate, a semiconductor active device formed in the substrate, a layer of low-k dielectric material, a first patterned conducting layer, a second patterned conducting layer, and a cap layer formed thereon. The low-k material layer is formed over the semiconductor device. The first conducting line is formed in the low-k material layer and connected to the semiconductor active device. The second conducting line is formed in the low-k material layer but not electrically connected to the semiconductor active device. The cap layer is formed over the low-k material layer, the first and second conducting lines. The cap layer includes silicon and carbon.