Abstract: A high-speed out-of-band signalling technique for transferring information such as station status information between stations in a communication network, typically a local-area network, involves sequentially generating a plurality of n-bit sequence segments, where n is at least 3. Each bit is either a first binary value or a second binary value. Each sequence segment is coded with one of a plurality of different n-bit code groups divided into a first code group and a set of second code groups. The n bits in the first code group are all the first binary value--e.g., all "1s". None of the second code groups contain a pair of non-contiguous bits of the second binary value--e.g., none of the second code groups contains two "0s" separated by at least one other bit. The sequence segments are outputted in the order that they were generated to produce a special bit sequence which carries the desired information.

Abstract: A data-transmitting apparatus contains first and second transmitters, a transmit transformer, and a connecting unit for coupling the transformer to an outgoing twisted-pair cable. The first transmitter filters data to produce outgoing data transmitted to the transformer at a first data rate. The second transmitter transmits outgoing data to the transformer at a different, typically greater, second data rate. A data-receiving apparatus contains first and second receivers, a receive transformer, and a connecting unit for coupling an incoming twisted-pair cable to the receive transformer. The first and second receivers receive incoming data from the secondary winding respectively at the first and second data rates. Incoming data is typically provided along data transfer paths that extend from the receive transformer in a daisy chain manner to the receivers. Data moving at either data rate can be transmitted and received without the need for hot switching in the data paths.

Abstract: A tri-state pin driver is formed in part, along with a pin sensor, on an integrated circuit. A pin driver and sensor are coupled to a common pin of a device under test. In normal mode, the pin driver drives a test signal. In high impedance mode, the pin driver is at a high impedance, enabling a sensor to monitor a response signal. The pin driver includes a driver stage formed off-chip by a pair of power transistors operated in the active region. The large power transistors enable a large current (i.e., +/-500 mA) to be sourced or sunk so as to drive a device under test and back-drive preceding circuits. Operating in the active region enables faster logic state transition times, and thus, a fast test rate, while reducing undesirable signal distortion. A predriver stage is configured as a unity-gain emitter follower. The predriver stage includes first and second signal paths. Each signal path includes a pair of transistors configured, during normal mode, as a transmission gate.

Abstract: A circuit for calibrating linear delay lines wherein a periodic ramp voltage is counted a fixed number of times at first and second frequencies. While the ramp voltages are being counted at each frequency, system clock pulses are counted. The number of system clock pulses counted for each first and second ramp voltage frequency is used to adjust the charging current applied to an integrator which establishes the delay value.